A method for consistent fault coverage reporting

IEEE Transactions on …, 1990

Proceedings of the conference on Design, …, 2001

The number of times a fault f in a combinational circuit is detected by a given test set T was shown earlier to affect the defect coverage of the test set. The earlier definition counted each test in T, that detects f, as a distinct detection of f. This definition counts two tests as distinct detections even if they differ only in the values of inputs that do not affect the activation or propagation of the fault. In this work, we introduce a stricter definition that requires that two counted tests would be different in the way they activate and/or propagate the fault. We describe procedures for constructing test sets based on the stricter definition, and compare them to test sets for the earlier, less strict definition. The results show a simple criterion to decide when it may be necessary to combine the two definitions in order to obtain a high quality test set.

IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 1993

The field reject ratio, the fraction of defective devices that pass the acceptance test, is a measure of the quality of the tested product. Although the assessment of quality is important, a n accurate measurement of the field reject ratio of tested VLSI chips is often not feasible. We show that the known methods of field reject ratio prediction are not accurate since they fail to realistically model the process of testing. We model the detection of a fault by a n input test vector as a random event. However, we recognize that the detection of a fault may be delayed for various reasons: the fault may be detectable only by application of a sequence of vectors or it may not have been targeted until later. In our statistical model, a fault is characterized by two parameters: a per-vector detection probability and an integer-valued latency. Irrespective of the detection probability, the fault cannot be detected by a vector sequence shorter than its latency. The circuit is characterized by the joint distribution of latency and detection probability over all faults. This distribution, obtained by applying the Bayes' rule to the actual test data, enables us to compute the field reject ratio. The sensitivity of this approach to variations in the measured parameters is also investigated.

1995

In this paper, a novel methodology for test preparation of digital ICs, aiming at high defect coverage and affordable computational e ort, is proposed. A method is presented to heuristically generate a list of pseudo realistic (PSE) faults, at gate level, such that test quality is improved when PSE faults are used in test generation, in addition to normal stuck-at testing. Test quality assessment is performed in the bottom-up phase, using layout data and extracted realistic faults. Experiments are performed using two new tools, tabloid and iceTgen. Simulation examples using ISCAS benchmarks demonstrate that PSE faults can be rewardingly used especially for I DDQ test generation, leading to very low escape rates.

Information Technology and Control, 2015

The design complexity of systems on a chip drives the need to reuse legacy or intellectual property cores, whose gate-level implementation details are unavailable. The core test depends on manufacturing technologies and changes permanently during a design lifecycle. In this paper we consider the impact of circuit realization on the fault coverage of the test set. We have performed various comprehensive experiments with combinational benchmark circuits. Our experiments show that the test sets generated for a particular circuit realization fail to detect in average only less than one and a half percent of the stuck-at faults of the re-synthesized circuit but in some cases this figure is more than nine percent. The double test sets declined almost twice both the maximum and the average percent of undetected faults. The experiments exhibit that the supplement of the test set with sensitive adjacent test patterns significantly increases the fault coverage of the re-synthesized core.

Journal of Electronic Testing, 1992

This paper presents a theoretical expression to evaluate the test quality of hierarchical defect-tolerant integrated circuits. This expression, which is developed for circuits with two levels of hierarchy, is based on a defect model with which one can take into account the relative importance (probability of occurrence) of each defect and consequently of each fault. Results obtained from this expression show that, for a given test coverage, the addition of defect-tolerance mechanisms decreases the test quality of integrated circuits. These results are important because they indicate that fault coverage can be a misleading measure of the test quality of defect-tolerant integrated circuits.

1999

Efficient methods to evaluate the quality of a test set in terms of its coverage of arbitrary defects in a circuit are presented. Our techniques rapidly estimate arbitrary defect coverage because they are independent of specific, physical, fault models. We overcome the potentially explosive computational requirements associated with considering all possible defects by implicitly evaluating multiple faults (of all types) simultaneously and by exploiting the local nature of defects. Our experiments show that a strong correlation exists between stuck-at fault coverage and defects whose behavior is independent of the input vectors. Our techniques are capable of identifying regions in the circuit where defects may escape the test set. We also demonstrate how the chances of detection of an arbitrary defect by a test set vary when a single stuck-at-fault within the vicinity of that defect is detected multiple times by the test set

In this paper we introduce a spectral method of register transfer level (RTL) test generation for sequential circuits. We define RTL faults as stuck-at faults on all primary inputs, primary outputs, and flip-flop terminals. Test vectors generated to cover the RTL faults are analyzed using Hadamard matrices. The analysis determines the amplitudes of prominent Walsh functions and the random noise level for each primary input. That information is then used to generate vectors for any gate-level implementation. At the gate-level, a fault simulator and an integer linear program (ILP) are used to compact the test sequence. We give results for three ITC'99 and four ISCAS'89 benchmark circuits. Each ITC'99 circuit was synthesized two ways, separately for area and delay optimization. The RTL spectral vectors performed equally well on both implementations. When compared to a gatelevel ATPG, the coverages of RTL vectors were similar and in many cases RTL vectors produced equal or higher coverage in shorter CPU time.

2000

Understanding the effectiveness of their production tests is a critical task for IC suppliers. Numerous trends suggesting that conventionally applied test methods must change to meet future needs will make the task even more critical – and difficult – in the future. This paper presents characterization and diagnostic data and ideas aimed at helping IC suppliers understand test effectiveness.

Software & Systems Modeling, 2014

Function block diagram (FBD), a graphical modeling language for programmable logic controllers, has been widely used to implement safety critical system software such as nuclear reactor protection systems. With the growing importance of structural testing for FBD models, structural test coverage criteria for FBD models have been proposed and evaluated using mutation analysis in our previous work. We extend the previous work by comprehensively analyzing the relationships among fault detection effectiveness, test suite size, and coverage level through several research questions. We generate a large number of test suites achieving an FBD test coverage ranging from 0 to 100 %, and we also generate many artificial faults (i.e. mutants) for the FBD models. Our analysis results show that the fault detection effectiveness of the FBD coverage criteria increases with increasing coverage levels, and the coverage criteria are highly effective at detecting faults in all subject models. Furthermore, the test suites generated with the FBD coverage criteria are more effective and efficient than the randomly generated test suites. The FBD coverage criteria are strong at detecting faults in Boolean edges, while relatively weak at detecting wrong constants in FBD models. Empirical knowledge regarding our experiments provide the validity of using the FBD coverage criteria, and therefore, of FBD model-based testing. Communicated by Dr. Perdita Stevens.