Filtering tricks for FSK demodulation

Experiment Objectives:

Radioengineering

The present article relates in general to digital demodulation of Binary Frequency Shift Keying (BFSK waveform) . New processing methods for demodulating the BFSK-signals are proposed here. Based on Sampler Correlator, the hardware consumption for the proposed techniques is reduced in comparison with other reported. Theoretical details concerning limits of applicability are also given by closed-form expressions. Simulation experiments are illustrated to validate the overall performance.

Frequency shift keying (FSK) is the most common form of digital modulation in the high-frequency radio spectrum. The demodulation of Binary FSK involves complex operations on the modulated signal like reconstruction of carrier signal and multiplication of carrier signal with the modulated signal. In this paper, BFSK is realized as two separate ASKs and a much simpler incoherent method is proposed for demodulation of BFSK modulated signal. Since power consumption is one of the main factors in electronic devices, low power devices are always demanding. Power Consumption could be minimized by reducing the actual block diagram of the system by opting an alternative approach to achieve the same output signal. The same BFSK demodulator can be used to demodulate an ASK modulated signal if it follow certain criteria's.

IEEE Journal of Solid-State Circuits, 2003

This paper presents a fully integrated highly sensitive frequency-shift keying (FSK) demodulator functioning at a modulation factor of 0.5%-0.1% and below. A dual-feedback phaselocked loop approach provides both very high sensitivity and sufficiently large tuning range. Experimental results in TSMC 0.25-m CMOS technology demonstrate that Gaussian FSK signals of a modulation factor down to 0.06% can safely be demodulated.

IEEE Journal on Selected Areas in Communications, 1990

An all-digital demodulator/detector is presented which is suitable for both analog FM and digital phase/frequency modulations. The system uses complex sampling, which employs a single A/D to sample the signal at an intermediate frequency (IF) and produce baseband in-phase ( I ) and quadrature phase ( Q ) signals, and a simplified technique for reducing the effect of the I / Q timing misalignment usually associated with this approach. The system also includes two detectors which operate simultaneously to provide noncoherent and differentially coherent detection, as well as automatic gain control (AGC) and automatic frequency control (AFC). The flexibility afforded by the two concurrent detectors in this all-digital system is shown to make it suitable for a wide range of applications. This paper describes the theory behind the demodulator/detector system and presents an implementation using a 1.25 pm bulk CMOS VLSI process. Methods are shown for extending and improving the I / Q sampling misalignment correction technique, as well as reducing the AID sampling rate for a given IF frequency. Simulation and experimental results are shown to illustrate system performance for both analog and digital modulations.

2014 International Telecommunications Symposium (ITS), 2014

This work presents a new structure for an alldigital BPSK demodulator developed for space communications that performs simultaneously the sampling and down conversion from intermediate frequency signal to the baseband signal. A new interpolator is proposed in order to simplify the demodulator implementation. This interpolator correlates the samples of the output signal in such way that it was necessary to design a new data detector appropriate to process the samples corrupted by gaussian and colored noise. The effects of the new interpolation at the noise are analyzed as well as the way it affects the whole demodulator performance. Simulations were performed and the results are presented to confirm theoretical analysis.

This paper deals with the design and implementation aspects of high data rate digital demodulators. The Existing remote sensing satellites support data rates of several hundred mega bits per second. The future trend is towards giga bit rate transmission. This necessitates for demodulators of the ground receive system to process faster and handle the ever-rising data throughput more efficiently. Different Satellites use different modulation schemes with variable data rates. In order to cater to the Multi mission /Multisatellite data reception requirements of a ground station, it is necessary to have greater flexibility and programmability features embedded in the design of demodulators. The demodulation techniques for Binary / Quadrature Phase shift Keying (BPSK/ QPSK) are well established and understood when implemented with analog circuits. The BPSK/ QPSK can be demodulated by different techniques such as squaring loop, Costas loop and others in analog domain. The Costas loop technique is adopted for developing the digital demodulator because unlike in Square Loop technique, in this the carrier recovery and data demodulation can be done simultaneously with simple blocks level design. The high data rate digital demodulator performs IF amplification, filtering and analog to digital conversion of the received IF signal followed by a Digital demodulator. The basic design strategy includes a configurable data rate BPSK/ QPSK demodulation with COSTAS loop circuitry utilizing the flexibility of FPGA implementation. The basic design considering a sampling clock from local clock oscillator operating at 125 MHz and 70 MHz carrier down converted to 30 MHz for 8 Mbps data rate (For BPSK). Later the sampling clock is increased to 250 MHz and the carrier is direct 70 MHz with data rate 42.4456 Mbps (For QPSK). The Performance of the Demodulator is evaluated using MATLAB simulation tools. The development has done with ISE implementation tools. The purpose of this paper is to evaluate the new technology by implementing a BPSK/QPSK demodulator on an ADC-FPGA board. A mathematical algorithm was developed and implemented with ISE tools for digital demodulator design. The input test signals from Modulation Simulators and signal generators have been interfaced to the FPGA board through Analog-To-Digital Converter (ADC). The recovered carrier output and I, Q demodulated data patterns have been verified through ISE tools and Wave Vision Software for FFT analysis.

Wireless transmissions are increasingly growing their data rates, and equipment is required to be faster and more flexible in order to cope with various digital modulation schemes used to reach these rates. A very widespread solution is the Software Defined Radio (SDR), whose modulation / demodulation methodology consists in programming either software in a dedicated processor (DSP), or logic in a programmable logic device (FPGA). This results in a high degree of versatility in the equipment because the same physical hardware can be used to implement different digital demodulations. This article shows the digital demodulation of RBDS (Radio Broadcast Data System) information transmitted along with commercial FM broadcast (88MHz – 108MHz) using a FPGA device that can be reprogrammed to tailor different modulations without changing the hardware.

1995

Major Department: Electrical Engineering Frequency modulation (FM) and demodulation techniques are well established and understood when implemented with analog circuits. Recently, state-of-the-art digital technology allows radio-frequency (RF) signals to be processed in the discrete-time domain. Modulated RF signals are digitally sampled and then demodulated in real time using signal processing techniques and a digital signal processor (DSP). A digital board capable of these tasks is often termed a "digital radio." This paper results from the availability of a digital radio board. The flexibility of DSP software allows a realization of different demodulation schemes. The purpose of this paper was to test this new technology by implementing an FM demodulator using the digital radio. A mathematical algorithm was developed and translated into DSP software to implement the "digital FM demodulator." The testing of the digital FM demodulator provided a performance analysis of the developed algorithm. This paper addresses the detailed background, ix development, and testing of a digital FM demodulator as implemented on a digital radio board.

Proceedings of the 2005 European Conference on Circuit Theory and Design, 2005., 2000

Personal communications require wireless nodes, which can transmit and receive reliably data under huge power constraints. Higher level of integration and reduction of power consumption can be achieved using a zero-IF architecture together with a wideband BFSK modulation scheme. Unfortunately FSK techniques performances degrade sharply in the presence of frequency offset. In this paper a comparison between potentially low power BFSK architectures is presented based on high level models. In depth analysis of four potentially low power demodulators shows that the architecture, which can assure rejection of large static offset with minimum increment in hardware complexity is the ST-DFT based demodulator. This will allow great reduction in power consumption avoiding acquisition and tracking of the offset at the receiver side.