Scalable Run Time Reconfigurable Architecture
Abdellah Touhafi2000, VLSI: Systems on a Chip
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Abstract
Currently multi-FPGA reeonfigurable eomputing systems are still eommonly used for accelerating algorithms. This teehnology where acceleration is aehieved by spatial implementation of an algorithm in reeonfigurable hardware has proven to be feasible. However, the best suiting algorithms are those who are very struetured, ean benefit from deep pipelining and need only loeal eommunieation resourees. Many algorithms ean not fulfil the third requirement onee the problem size grows and multi-FPGA systems beeome neeessary. In this paper we address the emulation of a run time reeonfigurable proeessor arehiteeture, whieh seales better for this kind of eomputing problems.
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