A Simple Architecture for Low Level Parallelism

1983

Recent developments in integrated circuit technology have suggested a new building block for parallel processing system::;: the single chip computer. This building block makes iL economically feaSible to interconnect large numbers of computers to ferm a muttiImcrocomputer network. Becat:.se the nodes of .men a network do not share any memory, it is Cl'llclUl that a inlerr,unneclion network capable of efficiently supporting message passing be found. We prp.sent a model of Lime varying computation based on task precedence graphs that corresponds closely to the beilav1rIl' of fork/join algorithms such as divide~nd conquer. Using thIS mond, we investigate the behavior f)f t:!ve interconncctiol~ndwod~s under varying "Workloads with distributed scheduling.

Concurrency: Practice and Experience, 1991

Although both shared memory and loosely coupled parallel computing systems are now common, many still do not offer an easy way to design, implement, and test parallel algorithms. Our system provides software tools that make possible a variety of connection structures between processes. These structures are said to form a 'Network Multi-Processor', which is implemented on a local area network of heterogeneous UNIX-based timesharing computers, plus a set of processor boards dedicated to an application so that accurate timing measurements can be made. We explain how these tools have been used both to aid parallel algorithm development and to explore the properties of different computer interconnection methods.

2009

2004

The design of parallel programs requires fancy solutions that are not present in sequential programming. Thus, a designer of parallel applications is concerned with the problem of ensuring the correct behavior of all the processes that the program comprises. There are different solutions to each problem, but the question is to find one, that is general. One possibility is allowing the use of asynchronous groups of processors. We present a general methodology to derive efficient parallel divide and conquer algorithms. Algorithms belonging to this class allow the arbitrary division of the processor subsets, easing the opportunities of the underlying software to divide the network in independent sub networks, minimizing the impact of the traffic in the rest of the network in the predicted cost. This methodology is defined by OTMP model and its expressiveness is exemplified through three divide and conquer programs.

Lecture Notes in Computer Science, 1996

E cient communication in networks is a prerequisite to exploit the performance of large parallel systems. For this reason much e ort has been done in recent years to develop e cient communication mechanisms. In this paper we survey the foundations and recent developments in designing and analyzing e cient packet routing algorithms. Organization of the Paper In the following chapter we introduce the basic notation about networks, messages, and protocols for routing. In Chapter 3 we introduce the routing number of a network, and relate it to the dilation and congestion of path systems. Chapter 4 contains an overview of oblivious routing protocols, and Chapter 5 describes e cient adaptive routing protocols. 2 Networks, Messages, Protocols In this chapter we introduce the basic notions used in routing theory. In particular, we describe a typically used hardware model and message passing model, de ne the routing problem, and describe di erent classes of strategies to solve routing problems. 2.1 The Hardware Model We model the topology of a network as an undirected graph G = (V; E). V represents the computers or processors, and E represents the communication links. We assume the communication links to work bidirectional, that is, each edge represents two links, one in each direction. The bandwidth of a link is de ned as the number of messages it can forward in one time step. Unless explicitly mentioned we assume that the bandwidth This article was processed using the L A T E X macro package with LLNCS style View publication stats View publication stats

Symposium on the Theory of Computing, 1982

1982

including computational physics, weather forecasting, etc. The current state of hardware capabilities will facilitate the use of such parallel processors to many more applications as the speed and the number of processors that can be tightly coupled increases dramatically. (A very good introduction to the future promise of "highly parallel computing" can be found in the January, 1982 issue of Computer, published by the IEEE Computer Society.)

Wiley-Interscience eBooks, 2004

Having covered the essential issues in the design and analysis of uniprocessors and pointing out the main limitations of a single-stream machine, we begin in this chapter to pursue the issue of multiple processors. Here a number of processors (two or more) are connected in a manner that allows them to share the simultaneous execution of a single task. The main argument for using multiprocessors is to create powerful computers by simply connecting many existing smaller ones. A multiprocessor is expected to reach a faster speed than the fastest uniprocessor. In addition, a multiprocessor consisting of a number of single uniprocessors is expected to be more cost-effective than building a high-performance single processor. An additional advantage of a multiprocessor consisting of n processors is that if a single processor fails, the remaining fault-free n 2 1 processors should be able to provide continued service, albeit with degraded performance. Our coverage in this chapter starts with a section on the general concepts and terminology used. We then point to the different topologies used for interconnecting multiple processors. Different classification schemes for computer architectures are then introduced and analyzed. We then introduce a topology-based taxonomy for interconnection networks. Two memory-organization schemes for MIMD (multiple instruction multiple data) multiprocessors are also introduced. Our coverage in this chapter ends with a touch on the analysis and performance metrics for multiprocessors. It should be noted that interested readers are referred to more elaborate discussions on multiprocessors in Chapters 2 and 3 of our book on Advanced Computer Architecture and Parallel Processing (see reference list).

International Conference on Parallel Processing, 1990