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2011, Information Processing Letters
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12 pages
1 file
We consider the relationship between size and depth for layered Boolean circuits, synchronous circuits and planar circuits as well as classes of circuits with small separators. In particular, we show that every layered Boolean circuit of size s can be simulated by a layered Boolean circuit of depth O(√ s log s). For planar circuits and synchronous circuits of size s, we obtain simulations of depth O(√ s). The best known result so far was by Paterson and Valiant [16], and Dymond and Tompa [6], which holds for general Boolean circuits and states that D(f) = O(C(f)/ log C(f)), where C(f) and D(f) are the minimum size and depth, respectively, of Boolean circuits computing f. The proof of our main result uses an adaptive strategy based on the two-person pebble game introduced by Dymond and Tompa [6]. Improving any of our results by polylog factors would immediately improve the bounds for general circuits.
Computational Complexity, 1995
Vie consider planar circuits, formulas and multilective planar circuits. It is shown that planar circuits and formulas are incomparable. An ~(n log n) lower bound is given for the multilective planar circuit complexity of a decision problem and an 12(n 3/2) lower bound is given for the multilective planar circuit complexity of a multiple output function.
Information Processing Letters, 1996
Journal of Statistical Mechanics: Theory and Experiment, 2011
Random instances of feedforward Boolean circuits are studied both analytically and numerically. Evaluating these circuits is known to be a P-complete problem and thus, in the worst case, believed to be impossible to perform, even given a massively parallel computer, in time much less than the depth of the circuit. Nonetheless, it is found that for some ensembles of random circuits, saturation to a fixed truth value occurs rapidly so that evaluation of the circuit can be accomplished in much less parallel time than the depth of the circuit. For other ensembles saturation does not occur and circuit evaluation is apparently hard. In particular, for some random circuits composed of connectives with five or more inputs, the number of true outputs at each level is a chaotic sequence. Finally, while the average case complexity depends on the choice of ensemble, it is shown that for all ensembles it is possible to simultaneously construct a typical circuit together with its solution in polylogarithmic parallel time.
We study Boolean circuits as a representation of Boolean functions and consider different equivalence, audit, and enumeration problems. For a number of restricted sets of gate types (bases) we obtain efficient algorithms, while for all other gate types we show these problems are at least NP-hard.
Information Processing Letters, 2004
From a theorem of Markov, the minimum number of negation gates in a circuit sufficient to compute any collection of Boolean functions on n variable is ℓ = ⌈log(n + 1)⌉. Santha and Wilson [SIAM Journal of Computing 22 : 294-302 (1993)] showed that in some classes of bounded-depth circuits ℓ negation gates are no longer sufficient for some explicitly defined Boolean function. In this paper, we consider a general class of bounded-depth circuits in which each gate computes an arbitrary monotone Boolean function or its negation. Our purpose is to extend the theorem of Markov for such a general class of circuits. We first show that a lower bound shown by Santha and Wilson becomes an extension of Markov's lower bound by a small refinement. Then, we present tight upper bounds on the number of negations for computing an arbitrary collection of Boolean functions.
Information Processing Letters, 2010
In this note, we present improved upper bounds on the circuit complexity of symmetric Boolean functions. In particular, we describe circuits of size 4.5n + o(n) for any symmetric function of n variables, as well as circuits of size 3n for MOD n 3 function.
Information and Control, 1984
Consider a family of boolean circuits C~, C2,..., C,,..., constructed by some uniform, effective procedure operating on input n. Such a procedure provides a concise representation of a family of parallel algorithms for computing boolean values. A formula of first-order logic may also be viewed as a concise representation of a family of parallel algorithms for evaluating boolean functions. The parallelism is implicit in the quantification (a formula gx q~(x) is true if and only if each of the formulas q~(a) is true, and all these formulas can be checked simultaneously), and universes of different sizes give rise to boolean functions with different numbers of inputs (the boolean values of the formula's predicates on various combinations of elements of the universe). This note presents an extended first-order logic designed to be exactly equivalent in expressiveness to polynomialsize, constant-depth, unbounded-fan-in circuits constructed by Turing machines of bounded computational complexity.
2002
Karchmer, Raz, and Wigderson, 1991, discuss the circuit depth complexity of n bit Boolean functions constructed by composing up to d = log n= log log n levels of k = log n bit boolean functions. Any such function is in AC 1. They conjecture that circuit depth is additive under composition, which would imply that any (bounded fan-in) circuit for this problem requires dk 2 (log 2 n= log log n) depth. This would separate AC 1 from NC 1. They recommend using the communication game characterization of circuit depth. In order to develop techniques for using communication complexity to prove circuit lower bounds, they suggest an intermediate communication complexity problem which they call the Universal Composition Relation. We give an almost optimal lower bound of dk O(d 2 (k log k) 1=2) for this problem. In addition, we present a proof, directly in terms of communication complexity, that there is a function on k bits requiring (k) circuit depth. Although this fact can be easily established using a counting argument, we hope that the ideas in our proof will be incorporated more easily into subsequent arguments which use communication complexity to prove circuit depth bounds.
Proceedings of the Twenty-Sixth Annual ACM-SIAM Symposium on Discrete Algorithms, 2014
We study algorithms for the satisfiability problem for quantified Boolean formulas (QBFs), and consequences of faster algorithms for circuit complexity. • We show that satisfiability of quantified 3-CNFs with m clauses, n variables, and two quantifier blocks (one existential block and one universal) can be solved deterministically in time 2 n−Ω(√ n) • poly(m). For the case of multiple quantifier blocks (alternations), we show that satisfiability of quantified CNFs of size poly(n) on n variables with q quantifier blocks can be solved in 2 n−n 1/(q+1) • poly(n) time by a zero-error randomized algorithm. These are the first provable improvements over brute force search in the general case, even for quantified polynomial-sized CNFs with two quantifier blocks. A second zero-error randomized algorithm solves QBF on circuits of size s in 2 n−Ω(q) • poly(s) time when the number of quantifier blocks is q. • We complement these algorithms by showing that improvements on them would imply new circuit complexity lower bounds. For example, if satisfiability of quantified CNF formulas with n variables, poly(n) size and at most q quantifier blocks can be solved in time 2 n−n ωq (1/q) , then the complexity class NEXP does not have O(log n) depth circuits of polynomial size. Furthermore, solving satisfiability of quantified CNF formulas with n variables, poly(n) size and O(log n) quantifier blocks in time 2 n−ω(log(n)) time would imply the same circuit complexity lower bound. The proofs of these results proceed by establishing strong relationships between the time complexity of QBF satisfiability over CNF formulas and the time complexity of QBF satisfiability over arbitrary Boolean formulas.
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