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2010, New Generation …
AI
This work discusses the Verilog language's constructs, specifically focusing on synthesizable hardware descriptions. It outlines three primary types of constructs: structural, behavioral, and elaborative. The importance of parameterized modules for creating flexible, reusable designs, such as a family of ripple adders, is emphasized. Additionally, the paper addresses the preservation of well-typed constructs during expansion in hardware design methodology.
Proceedings of the …, 2008
2007
Hardware description languages (HDL) suffer from inconsistencies between their simulation and synthesis semantics: A program successfully compiled and simulated might fail to synthesize. In this work, we propose the usage of statically typed two-level languages (STTL) to eliminate such inconsistencies.
2011 14th Euromicro Conference on Digital System Design, 2011
Synchronous hardware can be straightforwardly modelled as a function from input and (current) state to an updated state and output. The CλaSH compiler can translate such a transition function, described in a functional language, to synthesisable VHDL. Taking a hardware-oriented viewpoint, components can then be seen as an instantiation of such a transition function. An abstraction called Arrows is used to directly model components by combining a transition function and its state. The abstraction also provides an uniform interface for composition, without losing the referential transparency offered by a functional description. Furthermore, readability of hardware designs is increased by the use of the γ-syntax, that automatically composes components according to the Arrow interface. The advantages of the Arrow abstraction and the γ-syntax are demonstrated by means of a realistic example circuit consisting of multiple components. This is a significant extension to CλaSH and enables many high level abstractions.
Proceedings of the 13th International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies
Typical hardware description languages, such as Verilog and VHDL, are low-level declarative languages with little room for flexibility. Extending, verifying, or reinterpreting programs in these languages is typically done with external tools and at great cost. This paper presents an implementation of a relational hardware description language, Ruby, in the programming language and proof assistant Agda. Using our system, an engineer can easily write, compile, simulate, and verify new designs. The language is modular, allowing for new constructs and libraries to be added easily, and supports formal reasoning about circuit transformations. Symbolic simulation and compilation to a netlist format are also provided. We demonstrate our tool by designing, compiling, and simulating a priority queue design, and showcase how equational reasoning can be used to prove properties of circuits. CCS CONCEPTS • Hardware → Reconfigurable logic and FPGAs; • Software and its engineering → Domain specific languages; • Theory of computation → Program specifications.
2010
This paper describes a formal executable semantics for the Verilog hardware description language. The goal of our formalization is to provide a concise and mathematically rigorous reference augmenting the prose of the official language standard, and ultimately to aid developers of Verilogbased tools; e.g., simulators, test generators, and verification tools. Our semantics applies equally well to both synthesizeable and behavioral designs and is given in a familiar, operational-style within a logic providing important additional benefits above and beyond static formalization. In particular, it is executable and searchable so that one can ask questions about how a, possibly nondeterministic, Verilog program can legally behave under the formalization. The formalization should not be seen as the final word on Verilog, but rather as a starting point and basis for community discussions on the Verilog semantics.
IEE Proceedings E Computers and Digital Techniques, 1985
Chip designs should be produced by building from a large selection of appropriate component designs. Each component should be modular, but the resulting design should permit consistency checking. STRICT attempts to embody these principles in a formal notation for the design of integrated circuits.
A wide variety of application domains such as networking, computer vision, and cryptography target FPGA platforms to meet computation demand and energy consumption constraints. However, design effort for FPGA implementations in hardware description languages (HDLs) remains highoften an order of magnitude larger than design effort using high level languages (HLLs). Instead of development in HDLs, high level synthesis (HLS) tools generate hardware implementations from algorithm descriptions in HLLs such as C/C++/SystemC. HLS tools promise reduced design effort and hardware development without the detailed knowledge of the implementation platform. In this paper, we study AutoPilot, a state-of-the-art HLS tool, and examine the suitability of using HLS for a variety of application domains. Based on our study of application code not originally written for HLS, we provide guidelines for software design, limitations of mapping general purpose software to hardware using HLS, and future directions for HLS tool development. For the examined applications, we demonstrate speedup from 4X to over 126X, with a five-fold reduction in design effort vs. manual design in HDLs.
The design and analysis of embedded, mixed hardware/software systems, such as PC cards, application specific hardware, m-and e-commerce devices, mobile telecommunication infrastructure and associated software drivers, is hard. An important issue for correct codesign is the search for a highly compositional and unifying formal approach that crosses the hardware/software boundaries and enables us to keep up with the fast growth in the complexity and variety of electronic devices and their associated software. Hardware/software codesign is a relatively new discipline interconnecting several other fields of research such as Electronics Engineering and Computer Science with the earliest reference to codesign dated back to 1992. In this thesis, I describe an integrated compositional framework for codesign of mixed hardware/software systems, together with its underpinning theory of semantics and refinement. My work integrates formal methods into the design process and the focus of the thesis i ABSTRACT ii is on refinement from a formal specification into a formal hardware part and a formal software part. Central to my methodology is that the synthesis and design start with a single highlevel abstract specification which captures the desired behaviour(s) of the system. Decisions are then taken through correctness preserving refinement steps. I have given formal semantics to Verilog-a Hardware Description Language (HDL) conceived in and extensively used by the hardware industry-in both denotational (in specification-oriented style) and operational terms and my work on Verilog enables me to blend existing and commercially available hardware synthesis tools and methodologies into my formal framework. This has the benefit of linking software development with hardware development in an integrated fashion and therefore span the gap between hardware and software formally. The equivalence between the two forms of semantics is proven and a set of generic refinement laws is presented. A detailed case-study of a smart card application of the Rivest Shamir Adleman (RSA) encryption algorithm is provided to evaluate my approach.
In this paper we present a design tool for automatic synthesis of Verilog behavioral description of an asynchronous circuit into delay insensitive presynthesized library modules, using syntax directed techniques. Our design tool can also generate appropriate output to support implementing the circuit on ASICs and LUT-based FPGAs consequently rapid prototyping of the asynchronous circuit becomes readily available using the proposed tool.
Abstraction plays a critical role in verifying complex systems. A number of languages have been proposed to model hardware systems by, primarily, abstracting away their wide datapaths while keeping the low-level details of their control logic. This leads to a significant reduction in the size of the state space and makes it possible to verify intricate control interactions formally. These languages, however, require that the abstraction be done manually, a tedious and error-prone process. In this paper we describe Vapor, a tool that automatically abstracts behavioral RTL Verilog to the CLU language used by the UCLID system. Vapor performs a sound abstraction with emphasis on minimizing false errors. Our method is fast, systematic, and complements UCLID by serving as a back-end for dealing with UCLID counterexamples. Preliminary results show the feasibility of automatic abstraction and its utility in formal verification.
Lecture Notes in Computer Science, 2007
As first step, most model checkers used in the hardware industry convert a high-level register transfer language (RTL) design into a netlist. However, algorithms that operate at the netlist level are unable to exploit the structure of the higher abstraction levels, and thus, are less scalable. The RTL level of a hardware description language such as Verilog is similar to a software program with special features for hardware design such as bit-vector arithmetic and concurrency. We describe a hardware model checking tool, VCEGAR, which performs verification at the RTL level using software verification techniques. It implements predicate abstraction and a refinement loop as used in software verification. The novel aspects are the generation of new word-level predicates, an efficient predicate image computation in presence of a large number of predicates, and precise modeling of the bit-vector semantics of hardware designs.
Lecture Notes in Computer Science, 1995
In this paper, we propose a new approach to formal synthesis which focuses on the generation of verification-friendly circuits. Starting from a high-level implementation description, which may result from the application of usual scheduling and allocation algorithms, hardware is automatically synthesized. The target architecture is based on handshake processes, modules which communicate by a simple synchronizing handshake protocol. The circuits result from the application of only a few basic operations like synchronization, sequential execution or iteration of base handshake processes. Each process is guided by an abstract theorem that is used to derive proof obligations, to be justified after synthesis. Automation has been achieved to the extend that only those "relevant" proof obligations remain to be proven manually, e.g. theorems for data-dependent loops and lemmata about the used data types. The process-oriented implementation language is enriched by loop invariants. If those are given prior to the synthesis process and the underlying data types are only Booleans, i.e. finite-length bitvectors, then the complete synthesis and verification process runs automatically.
ACM Transactions on …, 1997
… Hardware Design and …, 1999
Abstract. Hardware description languages (HDLs) are used today to describe circuits at all levels. In large HDL programs, there is a need for source code reduction techniques to address a myriad of problems in formal verification, design, simulation, and testing. Program ...
Springer eBooks, 2014
A straightforward synthesis from functional languages to digital circuits transforms variables to wires. The types of these variables determine the bit-width of the wires. Assigning a bit-width to polymorphic and function-type variables within this direct synthesis scheme is impossible. Using a term rewrite system, polymorphic and function-type binders can be completely eliminated from a circuit description, given only minor and reasonable restrictions on the input. The presented term rewrite system is used in the compiler for CλaSH: a polymorphic, higherorder, functional hardware description language.
The Journal of supercomputing, 2001
2005
I propose a systematic review and evaluation of the use of general purpose, high-level programming languages for the design and synthesis of circuit specifications that implement algorithms directly as specialized hardware configurations. Specifically, I propose an examination of the, so-called, semantic gap between the understood features and semantics of popular software programming languages such as C and C++, and the capabilities of programmable logic devices such as FPGAs. A significant amount of research effort has already been devoted to this topic, but it is my belief that this research has generally failed to adequately address certain key issues in both principle and implementation. My research will comprise a study of the theory and practice of programming hardware descriptions, with the aim of providing insights that suggest how to bridge the semantic gap and yield more effective hardware programming techniques.
European Design and Test Conference, 1992
The paper discusses the problem of extending the use of VHDL to the field of hardware synthesis.The main difficulty lies in the fact that the semantics of standard VHDL is defined strictly in terms of simulation. We present a synthesis-oriented compiler based on a broad subset of VHDL. We describe the language subset, the internal design representation (based on an
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