Hardware-Software Cosynthesis for Digital Systems

2000

Abstract Current software and hardware co-synthesis methodologies of control dominated embedded systems focus primarily on improving productivity in the complex design process. In order to improve synthesis quality, we propose a methodology that incorporates data flow and control optimizations performed on a novel implementation independent design task representation. The approach is applicable to any co-synthesis tool; we use a public domain co-design environment to report some results of our investigation.

Design Automation for Embedded Systems, 2008

Hardware software co-synthesis process intends to determine an optimal architecture for an embedded application specified by a task graph or a specification language. In this paper, we present a cosynthesis approach targeting MPSoCs and distributed memory multiprocessor architectures for high performance embedded applications. Our co-synthesis approach produces pipelined multiprocessor architectures consisting of heterogeneous processing elements connected by a point-to-point communication structure. The co-synthesis process consists of four distinct phases; processing element selection for addition to the system, pipelined task allocation, scheduling and a regular interconnection topology mapping. Initially, an irregular topology is generated that is mapped to a regular architecture. Our co-synthesis methodology performs system partitioning and produces an irregular topology multiprocessor system. It also generates an optimal (or suboptimal) regular topology architecture after considering some of the well-known regular topologies like mesh, hypercube, tree, etc. The co-synthesis method is demonstrated by exploring embedded architectures for MPEG encoder and artificially generated application task graphs representing complex embedded systems.

1995

a dissertati o n submitted t o t he department o f e lectri c a l e n gineeri n g a n d t h e c o m m i t t e e o n g r a d u a t e s t u d i e s o f s t a n f o r d u n i v e r sity i np a r t i a l

1999

Abstract Current co-design methodologies of control dominated hardware software systems su er from inecient hardware HW and software SW synthesis of the various reactive system tasks. In order to improve synthesis quality, we propose a methodology that incorporates data ow in addition to control optimizations performed on a suitable task representation in a hardware and software co-design environment.

1992

Synthesis of systems containing application-specific as well as reprogrammable components, such as off-the-shelf microprocessors, provides a promising approach to realization of complex systems using a minimal amount of application-specific hardware while still meeting the required performance constraints. We describe an approach to synthesis of such hardware-software systems starting from a behavioral description as input. The input system model is partitioned into hardware and software components based on imposed performance constraints. Synchronization between various elements of a mixed system design is one of the key issues that any synthesis system must address. In this paper, we consider software and interface synchronization schemes that facilitate communication between system components.

1992

The authors formulate the synthesis problem of complex behavioral descriptions with performance constraints as a hardware-software co-design problem. The target system architecture consists of a software component as a program running on a re-programmable processor assisted by application-specific hardware components. System synthesis is performed by first partitioning the input system description into hardware and software portions and then by implementing each of them separately. The synthesis of dedicated hardware is then achieved by means of hardware synthesis tools (D.D. Mitchell, D.C.Ku, F. Mailhot, and T. Truong, `The Olympus Synthesis System for digital design' IEEE Design and Test Magazine, p.37-53, Oct. 1990), while the software component is generated using software compiling techniques. The authors consider the problem of identifying potential hardware and software components of a system described in a high-level modeling language and they present a partitioning procedure. They then describe the results of partitioning a network coprocessor

ABSTRACT This paper describes a parameterizable RISC processor core and its associated co-synthesis environment for embedding mixed hardware/software systems in sea-of-gates integrated circuits. The core is fully configurable so that the program and data memory sizes, the number and size of the I/O ports, the stack size and the number and type of its peripheral blocks can be automatically adjusted to the system requirements.

This article gives a design overview of the new hardware synthesis tool ConPro used for development of applicationspecific digital logic systems providing a high-level approach with imperative programming features filling the gap between hardware and software level. It is an experimental platform for studying different hybrid scheduling strategies, too. The ConPro development tool and programming language guides the user from an algorithmic programmer software view to RTL hardware architecture. Concurrency is explicitly modelled with communicating processes and interprocess communication primitives known from traditional and well-known parallel software development using leight weight processes (threads), like semaphores or mutexes. The process modell provides only a single control path resulting in strict sequential instruction scheduling. Concurrency inside processes is limited to the data path. Beneath explicitly modelled concurrency, automatic exploitation of inherent concurrency is provided by the synthesis compiler using a multi-pass hybrid scheduler.

2010

One of the key problems in complex digital system design is the rapid generation of efficient hardware functionality. The paper introduces an architecture template for targeting FPGA implementations as part of a dataflow based design flow for heterogeneous platforms, thereby allowing a designer to perform system level optimizations for consistent FPGA performance. The architecture provides scalable capabilities in both communications and processing allowing the core to be scaled to the problem size. Matrix ...

Abstract This paper describes a parameterizable RISC processor core developed in the scope of a co-synthesis environment for embedding mixed hardware/software systems in sea-of-gates integrated circuits. The core is fully configurable so that the program and data memory sizes, the number and size of the I/O ports, the stack size and the number and type of its periphera blocks can be automatically adjusted to the system requirements.