An efficient implementation of the 1D DCT using FPGA technology

In this paper we have designed high speed Adder based hardware efficient Discrete Cosine Transform (DCT) Algorithm, which process data in a sequential form at high data rate. We designed a novel DCT by using orthogonal property and compared with conventional DCT in terms of number of cells, cell area, leakage power, internal power, net power, switching power, delay and power delay product (PDP). In comparison with multiplier based conventional DCT and Adder based Conventional DCT, the net power dissipation is reduced by 32%. The proposed Adder based DCT net power Dissipation is reduced by 47% less and multiplier based proposed DCT is reduced by 38%. Here we have used Cadence RTL 180nm Technology to implement the design.

IEICE Transactions on Information and Systems, 2011

Conventional array processors randomly access input/coefficient data stored in memory many times during three-dimensional discrete cosine transform (3D-DCT) calculations. This causes a calculation bottleneck. In this paper, a 3D array processor dedicated to 3D-DCT is proposed. The array processor drastically reduces data swapping or replacement during the calculation and thus improves performance. The time complexity of the proposed N × N × N array processor is O(N) for an N 3-size input data cube, and that of the 3D-DCT sequential calculation is O(N 4). A specific I/O architecture, throughput-improved architectures, and more scalable architecture are also discussed in terms of practical implementation. Experimental results of implementation on FPGA (fieldprogrammable gate array) suggest that our architecture provides good performance for real-time 3D-DCT calculations.

Journal of Physics: Conference Series, 2018

This paper presents experimental results that compares between a full software (SW) implementation and a software/hardware (SW/HW) co-design implementation of a DSP algorithm on a Xilinx Zynq programmable System-on-chip (SoC). The case study being used is the 8x8 two-dimensional discrete cosine transform (2D DCT), present in the popular JPEG and MPEG4-AVC encoder. The full SW design is implemented on a hardcore ARM processor on the FPGA SoC. The SW/HW co-design utilizes both the ARM processor and the Configurable Logic Blocks (CLB) of the FPGA SoC, where the communication channel is implemented using the Xillybus FIFO buffers, implemented as an external DRAM. In this case, the core 2D DCT operations are executed on the CLB, while data initialization and transfers are implemented on the processor. Results show that SW implementation is faster compared to SW/HW implementation for data inputs of less than 0.48 megapixels. As data inputs get larger, SW/HW implementation shows better performance, with up to 2x faster for 2 megapixels data input size. This study proves the viability of implementing the 2D DCT operations as dedicated hardware accelerator in multimedia encoders.

International Conference on Acoustics, Speech, and Signal Processing,

A new class of practical fast algorithms is introduced for the Discrete Cosine 'nunsfom (DCT), a n important transform that is of particular interest i n image compression. For a n 8-point DCT only 11 multiplications and 29 additions are required. A systematic approach is presented to generate t h e different members in this class all having the same mini m u m arithmetic complexity. T h e structure of many of t h e published algorithms can be found in members of this class. An extension of t h e algorithm for longer transformations is presented. As a result, the 16-point DCT requires only SI multiplications a n d 81 additions, which is, to our knowledge, less t h a n t h e currently published algorithms.

In this paper, the implementation of a unified 8 × 8 discrete cosine transform (DCT) and its inverse is described. First, the accuracy of the structure that has been reported earlier is analyzed with Matlab in order to have internal word length requirements for the implementation. Then, the structure is modeled as a data path structure with Synopsys Module Compiler. When synthesizing the model with 19-bit internal word length onto 0.11 µm CMOS technology, the resulting pipeline exhibits an operation frequency of 253 MHz and uses 40 000 equivalent gates. The latency for both trans- forms is 94 cycles. Finally, the comparison to another unified pipeline structure reveals up to 15% smaller estimated area.

The existing algorithms for approximation of DCT targets only on the DCT of small transform lengths, the main objective is reducing the power and calculation time. Multiplications are the operations in DCT which consumes majority of time and power and it is very complex to calculate the values of DCT. Approximation is needed in DCT for higher transform lengths as computational complication increases non-linearly with higher size lengths DCT. To offer lower circuit complexity and superior compression performance Multiplier-free approximate DCTs have been implemented which can be easily implemented in VLSI hardware by using only addition operation and subtraction operations. Thus, compared to integer and conventional DCTs, approximated DCTs result in reduction of the chip area as well as in power consumption. In this paper, here an algorithm is presented for approximation of DCT where an approximate DCT of length N could be derived from pair of DCTs of length (N/2) at cost of N additi...

1994

Abstract The implementation of the two-dimensional discrete cosine transform (2D DCT) through the multiple onedimensional (row-by-column approach) and the direct 2D DCT is studied. It is observed that the execution times on different computer architectures using one-dimensional (1D) algorithms vary significantly although some of the examined algorithms have the same computational complexity (additions and multiplications). The direct 2D DCT outperforms all row-by-column approaches.

2011 International Conference on Devices and Communications (ICDeCom), 2011

Discrete cosine transform (DCT) is widely used in image and video compression standards. This paper presents distributed arithmetic (DA) based VLSI architecture of DCT for low hardware circuit cost as well as low power consumption. Low hardware cost is achieved by exploiting redundant computational units in recent literature. A technique to reduce error introduced by sign extension is also presented. The proposed 1-D DCT architecture is implemented in both the Xilinx FPGA and Synopsys DC using TSMC CLN65GPLUS 65nm technology library. For power and hardware cost comparisons, recent DA based DCT architecture is also implemented. The comparison results indicate the considerable power as well as hardware savings in presented architecture. 2-D DCT is implemented using row column decomposition by the proposed 1-D DCT architecture.

2011

An efficient algorithm and hardware implementation for a direct 2-D Discrete Cosine Transform (DCT) and inverse DCT is presented. A unique combination and sophisticated adaptation of algebraic integer encoding and butterfly structured algorithm is employed to achieve high troughput, bufferless, and multiplierless design. Eight 1-D 8 points DCT modules are employed each consists of so called modified 2-D algebraic integer encoding of a 1-D radix8 DCT. The scaling and quantizer-dequantizer modules are also improved by approximation method. These algorithmic improvements result in a bufferless, multiplierless, zero memory usage, and direct processing 2-D DCT and inverse DCT designs. Simulations with MATLAB and ModelSim softwares prove that the proposed design have maintained PSNR and MSE values compared to that of conventional design. The design is further improved by employing a 5 stages pipelined implementation. The pipelined implementation results in a higher clock frequancy with hi...

Proceedings IEEE International Conference on Application-Specific Systems, Architectures and Processors, 1997

The two-dimensional discrete cosine transform (2D-DCT) is at the core of image encoding and compression applications. We present a new architecture for the 2D-DCT which is based on row-column decomposition. An efficient architecture to compute the one-dimensional fast direct (1D-DCT) and inverse cosine (1D-IDCT) transforms, which is based in reordering the butterflies after their computation, is also discussed. The architectures designed exploit locality, allowing pipelining between stages and saving memory (in-place). The result is an efficient architecture for high speed computation of the (1D, 2D)-DCT that significantly reduces the area required for VLSI implementation.

IEEE Transactions on Signal Processing, 2000

A new fast algorithm for the type-II two-dimensional (2-D) discrete cosine transform (DCT) is presented. It shows that the 2-D DCT can be decomposed into cosine-cosine, cosine-sine, sine-cosine, and sine-sine sequences that can be further decomposed into a number of similar sequences. Compared with other reported algorithms, the proposed one achieves savings on the number of arithmetic operations and has a recursive computational structure that leads to a simplification of the input/output indexing process. Furthermore, the new algorithm supports transform sizes (1 2) (2 2), where 1 and 2 are arbitrarily odd integers, which provides a wider range of choices on transform sizes for various applications.

IEEE Transactions on Circuits and Systems for Video Technology, 2000

An area efficient row-parallel architecture is proposed for the real-time implementation of bivariate algebraic integer (AI) encoded 2-D discrete cosine transform (DCT) for image and video processing. The proposed architecture computes 8×8 2-D DCT transform based on the Arai DCT algorithm. An improved fast algorithm for AI based 1-D DCT computation is proposed along with a single channel 2-D DCT architecture. The design improves on the 4-channel AI DCT architecture that was published recently by reducing the number of integer channels to one and the number of 8-point 1-D DCT cores from 5 down to 2. The architecture offers exact computation of 8×8 blocks of the 2-D DCT coefficients up to the FRS, which converts the coefficients from the AI representation to fixed-point format using the method of expansion factors. Prototype circuits corresponding to FRS blocks based on two expansion factors are realized, tested, and verified on FPGA-chip, using a Xilinx Virtex-6 XC6VLX240T device. Post place-and-route results show a 20% reduction in terms of area compared to the 2-D DCT architecture requiring five 1-D AI cores. The area-time and area-time 2 complexity metrics are also reduced by 23% and 22% respectively for designs with 8-bit input word length. The digital realizations are simulated up to place and route for ASICs using 45 nm CMOS standard cells. The maximum estimated clock rate is 951 MHz for the CMOS realizations indicating 7.608•10 9 pixels/seconds and a 8×8 block rate of 118.875 MHz.

IEEE Transactions on Signal Processing, 1999

In this correspondence, an index permutation-based fast twodimensional discrete cosine transform (2-D DCT) algorithm is presented. It is shown that the N 2 N N 2 N N 2 N 2-D DCT, where N = 2 m N = 2 m N = 2 m , can be computed using only N N N 1-D DCT's and some post additions.

ijens.org

We propose a scalable architecture for a Discrete Cosine Transform (DCT) computation engine based on Single Instruction stream and Multiple Data stream (SIMD) -Array Processors. Each pixel of an input matrix is distributed across a 4-way connected Processing Element (PE); and a frame comprises several such PEs making it possible to compute as many pixels as the number of PEs in a frame. Tripling such frames allows us to compress a colored image as efficiently as any gray-scale image. We specifically target least possible computations by completely replacing a floating-point unit by Look-up-Tables (LUTs) and an efficient implementation of an 8-bit multiplier is presented. By making use of nine processors, arranged in a matrix of the order 3x3, we manage to compute nine coefficients in less than nine clock cycles resulting in a tremendous Data-Rate (DR) of 1.4Gbps at the cost of 967 slices. Performance is analyzed using SPARTAN III FPGA (Field Programmable Gate Array) and a comparison with a previously proposed systolic architecture is presented.

—The Discrete Cosine Transform, DCT forms a major backbone behind Image processing and Video Encoding/Decoding Applications. The DCT/IDCT Algorithm is a form of S imilarity Transform. This paper tries to analyze and discuss the motivation behind the development of the Fast Discrete Cosine Transform Algorithm based on Chen, Fralick et al, 1977[2], and C. Loeffler, Ligtenberg's Practical Fast 1D DCT Algorithms, 1984[3]. Techniques of Matrix Decomposition based on Folding, Rotation Matrices and Jacobi Diagonalization have been used to analyze the Decomposition. Further, a proof of concept is presented in the form of a handwritten optimized, Assembly Language implementation in ARM NEON Assembly is presented. This greatly optimizes the performance and improves processing. This paper is an attempt to explain the usage i n a lucid and effective language of computing.