Scalable Run Time Reconfigurable Architecture
Abdellah Touhafi1999, … of the IFIP TC10/WG10. 5 Tenth …
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Abstract
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The paper presents a scalable run time reconfigurable processor architecture designed to enhance performance in multi-FPGA systems, addressing the challenge of latency in communication between processing elements as problem complexity increases. It proposes a novel approach that leverages the fine granular nature of FPGAs to achieve better scalability and performance for high-level computational tasks. An emulator is developed to test this architecture using an ATM switch fabric simulator as a case study, demonstrating significant improvements over conventional meshed FPGA systems.
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