Layout Generation for Domain-Specific FPGAs

2004

When designing systems-on-a-chip (SoCs), a unique opportunity exists to generate custom FPGA architectures that are specific to the application domain in which the device will be used.

2011 International Conference on Field-Programmable Technology, 2011

Exploiting the benefits afforded by runtime partial reconfiguration (PR) on modern field-programmable gate arrays (FPGAs)requires PR-capable applications and associated PR-architectures, both of which are challenging tasks due to competing implementation metrics(e.g., area, power, operating frequency, etc.) and results in unmanageable design spaces. PR design space exploration (DSE) techniques and tools assist designers in efficiently and effectively exploring this design space. This paper presents the first, to the best of our knowledge, formulation-level PR DSE tool-FoRSE. FoRSE leverages the application's PR-architecture and mathematical FPGA device models and vendor-specified PR technology to generate Paretooptimal sets of PR-floorplans and devices based on designerdesignated implementation metrics. FoRSE can prune an application's implementation design space by three to four orders of magnitude in approximately 15 seconds.

2008 Ph.D. Research in Microelectronics and Electronics, 2008

This paper presents an automated method of generating an FPGA layout. The main purpose of developing a generator is to reduce the overall FPGA design time with limited area penalty. This generator works in two phases. In the first phase, it generates a partial layout using generic parameterized algorithms. The partial layout is generated to obtain a fast bitstream configuration mechanism, an efficient power routing and a balanced clock distribution network. In the second phase, the generator completes the remaining layout using automatic placer and router. This two-phase technique allows better maneuvering of the layout according to initial constraints. The proposed method is validated by generating the layout of an island-style FPGA which includes hardware support for the mitigation of Single Event Upsets (SEU). The FPGA layout is generated using a symbolic standard cell library which allows easy migration to any layout technology. This layout is successfully migrated to 130nm technology.

International Journal of Electronics, 2017

High-level design flow and environment for FPGA-based dynamic partial reconfiguration The main motivation of this paper is related to the lack of a high-level design flow for a partial dynamic reconfiguration management. Our contribution consists in proposing a high-level add-on methodology to the Xilinx's design flow for a dynamic partial reconfiguration. The main objective is to give an abstract view of the developed application in order to facilitate the designer task. The suggested design flow offers an application centric view on dynamic reconfiguration designs, which permits simplifying the optimization and generation of such designs. A new formulation of the reconfigurable modules' mapping process is put forward. This allows a design space exploration so as to find the convenient number of reconfigurable regions and their sizes as well as the reconfiguration sequence. A new tool was proposed to support our methodology by allowing creating and synthesizing graphical models of the developed application. We introduce a new block diagram to represent this latter and a sequence model that can be used for the design optimizations. To validate the proposed dynamic-partial-reconfiguration design environment, two application examples are given at the end of the paper. They demonstrate the usefulness of the suggested models and methods.

2007

High-level synthesis is becoming more popular as design densities keep increasing in both the ASIC and FPGA world. Additionally, modern programmable devices offer the advantage of partial reconfiguration, which allows an algorithm to be partially mapped into a small and fixed FPGA device that can be reconfigured at run time, as the mapped application changes its requirements. This paper presents resource constrained high-level synthesis heuristics, which utilize reconfigurable datapath components under a variety of implementation platforms. The resulting architectures can be shortened so that the gain in clock cycles outperforms the timing overhead of reconfiguration. The main advantage of the proposed methodology is that through run time reconfiguration, more complicated algorithms can be mapped into smaller devices without speed degradation.

Microprocessors and Microsystems, 2000

Dynamically Reconfigurable Field Programmable Gate Arrays (DR FPGAs) change many of the basic assumptions of what hardware is. DR FPGA-based dynamically reconfigurable computing has become a powerful methodology for achieving high performance while minimizing the resource required in the implementation of many applications. The key to harnessing the power of DR FPGAs for most applications is to develop high-level synthesis tools for transforming automatically an algorithmic level behavioral specification into DR FPGA configurations. In this paper we survey the current state-of-the-art in high-level synthesis techniques for dynamically reconfigurable systems. The differences in high-level synthesis technology between classical systems and dynamically reconfigurable systems are discussed. Then, we describe the basic tasks in the high-level synthesis of dynamically reconfigurable systems. Finally, techniques that have been developed in the past few years for the high-level synthesis of dynamically reconfigurable systems are presented. ᭧

Field-Programmable Logic and Applications, 2008

This paper describes and evaluates a method to generate partial FPGA configurations at run-time. The proposed technique is aimed at adaptive embedded systems that employ run-time reconfiguration to achieve high flexibility and performance. The approach is based on the availability of a library of partial bitstreams for a set of basic components. New partial configurations for circuits defined by netlists of basic components are created by merging together a default bitstream of the target area, the relocated configurations of the components, and the configurations of the switch matrices used for building the connections between the components. An implementation targeting the Virtex-II Pro platform FPGA is described. It runs on the embedded 300 MHz PowerPC CPU present in the FPGA. The proof-of-concept implementation was used to create partial configurations at run-time for 20 circuits with up to 21 components and 288 connections. The complete configuration creation process took between 7 s and 97 s.

2003

Reconfigurable systems fill the flexibility, performance, power dissipation, and development and fabrication cost gap between the application specific systems implemented with hard-wired application specific integrated circuits and systems based on the standard (general purpose) programmable microprocessors. During the last decade they became the mainstream implementation technology for custom computation and embedded system products in such fields as telecommunication, image processing, video processing, multimedia, DSP, cryptography, embedded control, etc. To efficiently develop, implement and use the reconfigurable systems, adequate computer-aided support tools are necessary. Since most reconfigurable systems are implemented using the look-up table (LUT) field programmable gate arrays (FPGA) technology, the circuit synthesis tools targeting this technology are of primary importance for their effective and efficient implementation. In this paper, a new sequential circuit synthesis methodology is discussed that targets LUT FPGAs and FPGA-based reconfigurable system-on-a-chip platforms. The methodology is based on the information-driven approach to circuit synthesis, general decomposition and theory of information relationship measures that we previously developed. Our synthesis methods considerably differ from all other known methods. The experimental results from the automatic circuit synthesis tools that implement our methods demonstrate that the informationdriven approach consistently applied in the whole sequential circuit synthesis chain efficiently produces very fast and compact sequential circuits.

Journal of Systems Architecture, 2012

This paper presents and evaluates a method of generating partial bitstreams at run-time for dynamic reconfiguration of sections of an FPGA. The method is intended for use in adaptive embedded systems that employ run-time reconfiguration to achieve high flexibility and performance. The proposed approach combines partial bitstreams of coarse-grained components to produce a new partial bitstream implementing a given circuit

2010 13th Euromicro Conference on Digital System Design: Architectures, Methods and Tools, 2010

This paper describes and evaluates a method to generate partial FPGA configurations at run-time. The proposed technique is aimed at adaptive embedded systems that employ run-time reconfiguration to achieve high flexibility and performance. The approach is based on the availability of a library of partial bitstreams for a set of basic components. New partial configurations for circuits defined by netlists of basic components are created by merging together a default bitstream of the target area, the relocated configurations of the components, and the configurations of the switch matrices used for building the connections between the components. An implementation targeting the Virtex-II Pro platform FPGA is described. It runs on the embedded 300 MHz PowerPC CPU present in the FPGA. The proof-of-concept implementation was used to create partial configurations at run-time for 20 circuits with up to 21 components and 288 connections. The complete configuration creation process took between 7 s and 97 s.