System-level synthesis using re-programmable components

1992

Synthesis of systems containing application-specific as well as reprogrammable components, such as off-the-shelf microprocessors, provides a promising approach to realization of complex systems using a minimal amount of application-specific hardware while still meeting the required performance constraints. We describe an approach to synthesis of such hardware-software systems starting from a behavioral description as input. The input system model is partitioned into hardware and software components based on imposed performance constraints. Synchronization between various elements of a mixed system design is one of the key issues that any synthesis system must address. In this paper, we consider software and interface synchronization schemes that facilitate communication between system components.

Microprocessors and Microsystems, 1986

Proceedings of the conference on Design, …, 2004

In this paper we analyse some methodological concerns that have to be faced in a design flow which contains automatic synthesis phases from high-level, system descriptions. In particular, the issues related to the synthesis of the communication between the system elements are considered. The context in which the analysis is performed is the design flow proposed in the ODETTE project: in this ambient, SystemC is exploited in order to provide efficient system-level models; after that, the SystemC+ SystemC subset and extensions can be used to get a refined description that, despite the use of object oriented features such as polymorphism and inheritance, can be automatically synthesised by means of the ODETTE tools. Still, the problem of interfacing the hardware synthesised with the other elements of the design (memories, peripherals) remains an important issue. In order to face this problem, we propose a pattern that can be used to design bus interfaces that allow both an high level of abstraction in the communication on the "user" side, and automatic synthesis by the ODETTE tools. In order to do this, OSSS global objects are exploited to implement the communication between the application and the interface. After presenting the general methodology, a specific library interface is presented, that could connect the device under design to a PCI bus. In order to prove the viability of the approach, an example of synthesis of an example, from the system level down to the RT level is performed.

1999

Abstract Current co-design methodologies of control dominated hardware software systems su er from inecient hardware HW and software SW synthesis of the various reactive system tasks. In order to improve synthesis quality, we propose a methodology that incorporates data ow in addition to control optimizations performed on a suitable task representation in a hardware and software co-design environment.

Proceedings EURO-DAC '96. European Design Automation Conference with EURO-VHDL '96 and Exhibition

This paper describes the theory and implementation of a novel system for hardware synthesis from requirement specifications expressed in a graphical specification language called Symbolic Timing Diagrams (STD). The system can be used together with an existing formal-verification environment for VHDL leading to a novel methodology based on the combination of synthesis and formal verification. We show the feasibility of the approach and experimental results obtained with the system on the well known example of an industrial production cell, where both FPGA and ASIC hardware implementations were successfully synthesized.

IEEE Transactions on Computers, 1982

This part of the research involves the design and implementation of a data-memory allocator, consisting of a set of algorithms and data structures which synthesize hardware at the logical level from an ISPL language description. Preliminary results indicate the allocator's performance compares favorably with a human designer when designing an elevator controller and a reduced PDP-8/E. 1.0 INTRODUCTION The motivation behind the research described in this paper is to enhance the digital designer's capabilities by producing more powerful design tools. Digital logic design has progressed to the point that the operation of the logic can be functionally expressed by a variety of hardware descriptive languages, ISP being one of the more widely used behavioral languages. Functional simulators exist and are useful for verifying system operation and performance measurements (Barb77a). Thus, the state of the art in digital design is such that the next addition to design aids should be a synthesis program; a program that can design the STRUCTURE of a digital system, given its FUNCTION or The research described in this paper was supported by the U.S. Army Research Office under grant DAAG29-76-G-0224, and by a fellowship from IBM Corporation. A

2009 12th Euromicro Conference on Digital System Design, Architectures, Methods and Tools, 2009

The deployment of a system application over a hardware architecture is a costly phase in the design process. This cost increases when dealing with complex applications in terms of computation requirements and exchange of data and for advanced architectures with complex and configurable communication infrastructures. The usage of abstract models for application, architecture and mapping is a key element for automatic hardware/software code generation and for the final deployment. In this paper, we present languages for abstract modeling of application, architecture, meta-mapping and mapping and we introduce a code generation flow. The use of those models allows the extraction and exploitation of architectural and application information for specific code generation to a target platform. A case study of modeling and deploying a complex 4G telecommunication application on a heterogeneous and multi core platform is presented. I.

Proceedings Design, Automation and Test in Europe. Conference and Exhibition 2001, 2001

Having to cope with the continuously increasing complexity of modern digital systems, hardware designers are considering more and more seriously language based methodologies for parts of their designs. Last year, the introduction of a new language for hardware descriptions, the SystemC C++ class library, initiated a closer relationship between software and hardware descriptions and development tools. This paper presents a synthesis environment and the corresponding synthesis methodology, based on traditional compiler generation techniques, which incorporate SystemC, VHDL and Verilog to transform existing algorithmic software models into hardware system implementations. Following this approach, reusability of software components is introduced in the hardware world and timeto-market is decreased, as shown by experimental results.

Proceedings of the IEEE, 2000

A&mct-'Ihe complexity of the circuit that can fit on an integrated drcuit (IC) chip has reached the level of a million -t o r s with the advent of Very-LugtscJe Integration Several automatic synthesis systems have evolved that "rid" the human designer m mauaging this complexity. This paper surveys such efforts. The synthesis is viewed as the process of transforming a highhel design spedkation into a lower level design spedticatioo that indudes m a stmctud details, leading to the physical design of the IC. The characteriatia of ten automatic synthesis systems are summari zed.

1995

a dissertati o n submitted t o t he department o f e lectri c a l e n gineeri n g a n d t h e c o m m i t t e e o n g r a d u a t e s t u d i e s o f s t a n f o r d u n i v e r sity i np a r t i a l

23rd ACM/IEEE Design Automation Conference, 1986

IEEE Design & Test of Computers, 1989

Digital signal processing is a key technology with applications in commercial a n d military electronic systems. Automation in the design of signal processors is needed to reduce the overall product development cycle a n d cost. The a u t h o r s report o n work done a t GE to address the design of DSP syst e m s through the u s e of high-level synthesis tools. The key to success i n hardware synthesis i s to have the application drive the tool development a n d to focus synthesis algorithms to a well-defined hardware architecture or class of architectures.

Data process algorithms are increasing in complexity especially for image and video coding. Therefore, hardware development using directly hardware description languages (HDL) such as VHDL or Verilog is a difficult task. Current research axes in this context are introducing new methodologies to automate the generation of such descriptions. In our work we adopted a high level and target-independent language called CAL (Caltrop Actor Language). This language is associated with a set of tools to easily design dataflow applications and also a hardware compiler to automatically generate the implementation. Before the modifications presented in this paper, the existing CAL hardware back-end did not support some high-level features of the CAL language. Consequently, highlevel designed actors had to be manually transformed to be synthesizable. In this paper, we introduce a general automatic transformation of CAL descriptions to make these structures compliant and synthesizable. This transformation analyses the CAL code, detects the target features and makes the required changes to obtain synthesizable code while keeping the same application behavior. This work resolves the main bottleneck of the hardware generation flow from CAL designs.

IEEE Design & Test of Computers, 1993

As the complexity of system design increases, use of pre-designed components, such as generalpurpose microprocessors, provides an effective way to reduce the complexity of synthesized hardware. While the design problem of systems that contain processors and ASIC chips is not new, computeraided synthesis of such heterogeneous or mixed systems poses challenging problems because of the differences in model and rate of computation by application-specific hardware and processor software. In this article, we demonstrate the feasibility of achieving synthesis of heterogeneous systems which uses timing constraints to delegate tasks between hardware and software such that the final implementation meets required performance constraints.