Simulation study of Double gate FinFETs using different HIGH-K

Communications on Applied Electronics, 2015

In this paper an n-type double gate FinFET at a gate length of 22nm is reported. Here the device performance of FinFET under different gate materials and also under different buried oxides is construed. Firstly, the drain current under different gate materials, with different work functions and SiO 2 being the buried oxide has been obtained. A transfer characteristic curve has then been obtained comparing the drain current for different gate materials at a given supply voltage of 0.5 V. Secondly, the transfer characteristic curve, comparing the drain currents obtained under different buried oxides at 0.5 V supply voltage with Aluminium being the gate has been obtained. And lastly obtained is the device performance for different combinations of gate materials and buried oxides and the results were compared. It can be inferred that, a metal gate and a high k dielectric is what gives a good performance at nanometre ranges. All the simulations have been done in Visual TCAD.

International Journal on Intelligent Electronic Systems, 2007

FinFET is a novel double-gate device structure for future device design, modeling and circuit simulation purposes. FinFET have high-performance and low leakage, fully depleted silicon-on-insulator (FDSOI) device, which have been demonstrated down to 15 nm gate length and are relatively simple to fabricate, which can be scaled to gate length below 10 nm. In this paper the modeling of potential and current is carried out. Further the theoretical aspects of the series resistance, reliability issues, process variation effects and device scaling limits are also described for this device.

IEEE Transactions on Electron Devices, 2002

Design considerations of FinFET have been investigated by three-dimensional (3-D) simulation and analytical modeling in this paper. Short-channel effects (SCE) of FinFET can be reasonably controlled by reducing either silicon fin height or fin thickness. Analytical solution of 3-D Laplace's equation is employed to establish the design equations for the subthreshold behavior in the fully depleted silicon fins. Based on the 3-D analytical electrostatic potential in the subthreshold region, the threshold voltage ( ) roll-off and the subthreshold swing ( ) are estimated by considering the source barrier changes in the most leaky channel path. roll-off is an exponential function of the ratio of effective channel length to drain potential decay length, which can then be expressed as a function of the fin thickness, the fin height and the gate oxide thickness. The drain-potential decay lengths of single-gate fully depleted SOI MOSFET (FDFET), double-gate MOSFET (DGFET), rectangular surrounding-gate MOSFET (SGFET), and FinFET are compared. The drain potential scaling length and roll-off can be included into a universal relation for convenient comparison. Index Terms-Double-gate MOSFET, FinFET, short-channel effects, silicon-on-insulator (SOI).

The MOSFET device performance deteriorates when it is scaled down to 45nm node and an alternative device structure being studied. FinFETs are the alternative new device structure, which replaces the MOSFET. The comparative study of Double Gate MOSFET (DGMOSFET), Tri-gate Fin Field Effect Transistor (FinFET) and Gate All Around (GAA) FinFET structures has been done for 22nm and 16nm technologies. The study is based on the ground of logic performance parameters which are I on /I off current ratio, Drain Induced Barrier Lowering (DIBL), Subthreshold Swing (SS) and Threshold voltage (V t) roll-off. These parameters are also termed as Short Channel Effects (SCEs) and for a nanoscale device performance these parameters needs to be controlled. The parameters are evaluated for various high-k dielectric materials. The high-κ dielectric Hafnium oxide (HfO 2) exhibits the best material to minimize SCEs for GAA structures. The aforementioned devices are also tested for transconductance (g m) which is an analog performance parameter. The accuracy of the results has been verified by 3-D SILVACO ATLAS. Keywords-Drain Induced Barrier Lowering (DIBL), double gate MOSFET (DGMOSFET), Fin Field Effect Transistor (FinFET) and Gate All Around (GAA), Ion/Ioff ratio, Subthreshold Swing (SS), Transconductance (g m).

Turkish Journal of Computer and Mathematics Education (TURCOMAT), 2021

This paper proposed on basis of a perimeter-weighted-sum method for the construction of a 3D-Analytical Modeling of double metalFin structure TFET with dual hetero gate oxide structure. The DM model device dividing into a symmetrical and asymmetrical dual-gate TFETs, and then resolving 3D architectures. The surface potential and the electrical field (E) achieved by resolving the Poisson 3D equation. The drain current (ID) is eventually calculated using Kane tunneling model to calculate the tunneling generation rate. Threshold voltage model also developed based on the charge inversion model. The performance analysis of dual hetero gate oxide Fin TFET device together with dual dielectric engineering techniques results in enhanced drain current and reduced SCE’s of low leakage current, threshold voltage roll-off and drain induced barrier lowering.

Active and Passive Electronic Components

Technology scaling below 22 nm has brought several detrimental effects such as increased short channel effects (SCEs) and leakage currents. In deep submicron technology further scaling in gate length and oxide thickness can be achieved by changing the device structure of MOSFET. For 10–30 nm channel length multigate MOSFETs have been considered as most promising devices and FinFETs are the leading multigate MOSFET devices. Process parameters can be varied to obtain the desired performance of the FinFET device. In this paper, evaluation of on-off current ratio (Ion/Ioff), subthreshold swing (SS) and Drain Induced Barrier Lowering (DIBL) for different process parameters, that is, doping concentration (1015/cm3 to 1018/cm3), oxide thickness (0.5 nm and 1 nm), and fin height (10 nm to 40 nm), has been presented for 20 nm triangular FinFET device. Density gradient model used in design simulation incorporates the considerable quantum effects and provides more practical environment for dev...

2014 Students Conference on Engineering and Systems, 2014

On scaling the conventional MOSFET in submicrometer regime, the short channel effects (SCEs) deteriorates the device performance. Owing to a new device structure (FinFET) has been introduced. This paper presents the effect of variation in different parameters of FinFET such as structure, dimension, doping and oxide material used for various electrical characteristics (on-state current (I on), Subthreshold Swing (SS), off-current (I off) and threshold voltage (V t)). As we increase the no. of gates in FinFET device, much better control of channel is obtained than the conventional MOSFET and SCEs are reduced to a great extent while scaling the device beyond32 nm regime. The comparison has been drawn on 3-D SILVACO ATLAS simulations for different FinFET structures, based on simulation results Cylindrical-Gate All Around (Cy-GAA) FinFET exhibits the higher I on current, smaller I off current, and high I on /I off ratio due to its symmetrical structure and removal of corner effects.

International Journal of Electrical and Computer Engineering (IJECE), 2022

This paper studies the impact of fin width of channel on temperature and electrical characteristics of fin field-effect transistor (FinFET). The simulation tool multi-gate field effect transistor (MuGFET) has been used to examine the FinFET characteristics. Transfer characteristics with various temperatures and channel fin width (W F =5, 10, 20, 40, and 80 nm) are at first simulated in this study. The results show that the increasing of environmental temperature tends to increase threshold voltage, while the subthreshold swing (SS) and drain-induced barrier lowering (DIBL) rise with rising working temperature. Also, the threshold voltage decreases with increasing channel fin width of transistor, while the SS and DIBL increase with increasing channel fin width of transistor, at minimum channel fin width, the SS is very near to the best and ideal then its value grows and going far from the ideal value with increasing channel fin width. So, according to these conditions, the minimum value as possible of fin width is the preferable one for FinFET with better electrical characteristics.

AEU - International Journal of Electronics and Communications, 2019

This paper is about the compared performance investigation of various structures of Hetero-Dielectric (HD) triple-gate FinFETs with different gate oxides in terms of Double Hetero Gate Oxide (DHGO), Triple Hetero Gate Oxide (THGO) and Quadruple Hetero Gate Oxide (QHGO) to produce lower leakage current, higher Ion/Ioff ratio, higher gm/gd and also lower Drain Induced Barrier Lowering (DIBL) than those of a conventional triple-gate FinFET. Among all of them, the best results are explored for the DHGO FinFET structure. In DHGO FinFET structure, a high-κ dielectric (κ =22) is used on the top oxide to increase the gate control and a low-k dielectric (κ =3.9) is used over silicon body owing to the compatibility of lattice constant of SiO2 and silicon. Mode-space drift-diffusion (DD_MS) model coupled with Schrodinger equation has been utilized in order to analyze the proposed and conventional structures in three dimensional (3D) simulation domain. Interestingly, by decreasing the thickness of the oxide layer and increasing the permittivity coefficient, the leakage current decreases, thus increasing the Ion/Ioff ratio. The DHGO FinFET structure is found to exhibit higher Ion/Ioff, lower DIBL and higher gm/gd ratio, thus proving performance superiority over the other conventional junctionless FinFET and also MOSFETs.

Trans stellar journals, 2021

We have been simulated the electrical characteristics of a 3-D silicon on insulator (SOI)triple gate (TG) nFinFET with a channel length of 5nm. Different gate dielectric materials have been used in this simulation with the help of SILVACO TCAD tools. The gate materials are SiO2, Si3N4, ZrO2, HfO2 and TiO2. The electrical characteristics such as threshold voltage, ON current (ION), OFF current (IOFF), ratio of On-Off current, Subthreshold slope (SS), drain induced barrier lowering (DIBL) and transconductance (gm) have been simulated. After analyzing the simulations, we have seen that high permittivity (k=40) of gate material (TiO2) gives improve values ofthreshold voltage, subthreshold swing, on-off current ratio, transconductance in comparison with other dielectric SiO2, Si3N4, ZrO2, and HfO2.Finally, the high k dielectric materials have a better option in the fabrication of TG FinFET device in future.