On turbo-schedules for LDPC decoding

Carpathian Journal of Electronic and Computer Engineering, 2017

Several modern error-correcting codes can perform close to the Shannon limit thanks to the turbo principle applied in their iterative decoding algorithms. In this paper the principle is discussed in relation to LDPC codes and turbo codes. Methods for improvement of both these codes are described, namely removal of short cycles for LDPC codes and trellis termination for turbo codes. Performance of reference LDPC and turbo codes with and without these improvements is simulated and compared.

2004

Abstract An efficient decoding schedule for low-density parity-check (LDPC) codes that outperforms the conventional approach, in terms of both complexity and performance, is presented. Conventionally, in each iteration, all symbol nodes and, subsequently, all the check nodes, send messages to their neighbors (" flooding schedule"). In contrast, in the proposed method, the updating of nodes is performed according to a serial schedule which propagates the information twice as fast.

IEEE Workshop on Signal Processing Systems

In this paper, we propose a turbo decoding messagepassing (TDMP) algorithm to decode regular and irregular lowdensity parity-check (LDPC) codes. The TDMP algorithm has two main advantages over the commonly employed two-phase messagepassing algorithm. First, it exhibits a faster convergence behavior (up to 50% less iterations), and improvement in coding gain (up to an order of magnitude for moderate-to-high SNR and small number of iterations). Second, the corresponding decoder architecture has a significantly reduced memory requirement that amounts to a savings of (75 + 25n/ C node-degrees)% > 75% for code-length n. A decoder architecture featuring the TDMP algorithm is also presented. Furthermore, we propose a new structure on the paritycheck matrix of an LDPC code based on permutation matrices aimed at reducing interconnect complexity and improving decoding throughput. In addition, we construct a wide range of LDPC codes based on Ramanujan graphs which possess this structure.

2006

Abstract Serial decoding schedules for low-density parity-check (LDPC) codes are described and analyzed. Conventionally, in each iteration all the variable nodes and subsequently all the check nodes send messages to their neighbors (¿ flooding schedule¿). In contrast, in the considered methods, the updating of the nodes is implemented according to a serial schedule. The evolution of the decoding algorithm¿ s computation tree under serial scheduling is analyzed.

2007

Abstract Conventionally, in each low-density parity-check (LDPC) decoding iteration all the variable nodes and subsequently all the check nodes send messages to their neighbors (flooding schedule). An alternative, more efficient, approach is to update the nodes' messages serially (serial schedule). A theoretical analysis of serial message passing decoding schedules is presented. In particular, the evolution of the computation tree under serial scheduling is analyzed.

IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2003

A high-throughput memory-efficient decoder architecture for low-density parity-check (LDPC) codes is proposed based on a novel turbo decoding algorithm. The architecture benefits from various optimizations performed at three levels of abstraction in system design-namely LDPC code design, decoding algorithm, and decoder architecture. First, the interconnect complexity problem of current decoder implementations is mitigated by designing architecture-aware LDPC codes having embedded structural regularity features that result in a regular and scalable message-transport network with reduced control overhead. Second, the memory overhead problem in current day decoders is reduced by more than 75% by employing a new turbo decoding algorithm for LDPC codes that removes the multiple checkto-bit message update bottleneck of the current algorithm. A new merged-schedule merge-passing algorithm is also proposed that reduces the memory overhead of the current algorithm for low to moderate-throughput decoders. Moreover, a parallel soft-input-soft-output (SISO) message update mechanism is proposed that implements the recursions of the Balh-Cocke-Jelinek-Raviv (BCJR) algorithm in terms of simple "max-quartet" operations that do not require lookup-tables and incur negligible loss in performance compared to the ideal case. Finally, an efficient programmable architecture coupled with a scalable and dynamic transport network for storing and routing messages is proposed, and a full-decoder architecture is presented. Simulations demonstrate that the proposed architecture attains a throughput of 1.92 Gb/s for a frame length of 2304 bits, and achieves savings of 89.13% and 69.83% in power consumption and silicon area over state-of-the-art, with a reduction of 60.5% in interconnect length. Index Terms-Low-density parity-check (LDPC) codes, Ramanujan graphs, soft-input soft-output (SISO) decoder, turbo decoding algorithm, VLSI decoder architectures. I. INTRODUCTION T HE PHENOMENAL success of turbo codes [1] powered by the concept of iterative decoding via message-passing has rekindled the interest in low-density parity-check (LDPC) codes which were first discovered by Gallager in 1961 [2]. Recent breakthroughs to within 0.0045 dB of AWGN-channel capacity were achieved with the introduction of irregular LDPC codes in [3], [4] putting LDPC codes on par with turbo codes. However, efficient hardware implementation techniques of turbo decoders have given turbo codes a clear advantage Manuscript

2010 National Conference On Communications (NCC), 2010

Turbo codes and Low Density Parity Check (LDPC) codes have been shown to be practical codes that can approach Shannon capacity in several communication systems. In terms of performance and implementation complexity, LDPC codes and turbo codes are highly comparable, especially at coding rates around 1/2. In many recent wireless standards such as 3GPP LTE and WiMax, both turbo and LDPC codes have been recommended at the encoder. However, the decoder for turbo codes involves trellises and the BCJR algorithm, while the decoder for LDPC codes uses sparse graphs and the message passing algorithm. Therefore, in several implementations, a designer is forced to implement either the turbo decoder or the LDPC decoder. The main idea behind this work is to enable the implementation of both decoders using a common architecture. We view the constituent convolutional code in a turbo code as a block code, and construct a sparse parity check matrix for it. Then, the sparse matrix and the associated bipartite graph are used for decoding the convolutional code by soft message passing algorithms. Simulation results show a manageable degradation in performance with a reduction in complexity.

… Communications Conference, 2008 …, 2008

The performance of a system with a quasi-cyclic lowdensity parity-check code is examined under various constraints on the decoding delay. Two alternatives are considered for the message-passing decoding algorithm: the sumproduct algorithm and the turbo-decoding message-passing algorithm. It is shown that their relative performance depends heavily on the stringency of the delay constraint; the TDMP algorithm results in substantially better performance than the SPA if the constraint is stringent.

IEEE Transactions on Communications, 2000

Low-Density Parity-Check (LDPC) codes are usually decoded by running an iterative belief-propagation (BP), or message-passing, algorithm over the factor graph of the code. The traditional message-passing scheduling, called flooding, consists of updating all the variable nodes in the graph, using the same pre-update information, followed by updating all the check nodes of the graph, again, using the same pre-update information. Recently, several studies show that sequential scheduling, in which messages are generated using the latest available information, significantly improves the convergence speed in terms of number of iterations. Sequential scheduling introduces the problem of finding the best sequence of message updates. We propose Informed Dynamic Scheduling (IDS) strategies that select the message-passing schedule according to the observed rate of change of the messages. In general, IDS strategies require computation to select the message to update but converge in fewer message updates because they focus on the part of the graph that has not converged. Moreover, IDS yields a lower errorrate performance than either flooding or sequential scheduling because IDS strategies overcome traditional trapping-set errors. This paper presents IDS strategies that address several issues including performance for short-blocklength codes, complexity, and implementability.

A complexity reducing method for iterative message passing decoding algorithms of Low-Density Parity-Check (LDPC) codes is described. It is based on lazy scheduling which involves a partial update of messages in the iterations. A Density Evolution (DE) approach is developed for optimization of the parameters for choice of the messages to be updated. Combined with an efficient serial scheduling, the resulting method reduces the decoding complexity by about 70-75% compared to the classical Belief Propagation (BP) scheme, while maintaining the same performance.