Comparison and analysis of various low power SRAM cells

The need for low power integrated circuits is well known because of their extensive use in the electronic portable equipments. On chip SRAMs (Static Random Access Memory) determine the power dissipation of SoCs (System on Chips) in addition to its speed of operation. Hence it is very important to have low power SRAMs. From the last more than five decades we are scaling down the size of the CMOS devices to make the devices portable and compact in size and to get better performance in terms of access time, power dissipation, delay etc. Thus the demand for low size and low power memory has increased. Working on low supply voltage and leakage energy has become main concern as the power consumption can be reduced significantly. As the IC process technology scales, the oxide thickness and operating voltage continues to decrease. Lower operating voltage will lower the stability of SRAM cell resulting in lower value of static noise margin. Power consumption and the speed are the major factors of concern for designing a chip along with the leakage power. The consumption of power and speed of SRAMs are some important issues among a number of factors that provides a solution which describes multiple designs that minimize the consumption of power and this article is also based on that. This article presents the simulation of 6T, 8T and 9T SRAM cells using low power reduction techniques and develops a modified model that provides the consumer with a product that costs less and having reduced power delay product. We, in our work, have designed and compared SRAM cells under different configurations (6T, 8T & 9T) on the basis of read and write delay, leakage power consumption and stability i.e., noise margins. We have also proposed a 7T SRAM cell which has better performance metrics with existing memory cells. All the simulation work had been carried out using Eldo SPICE tool of Mentor Graphics.

This paper discusses the basic operations of SRAM such as write, read and hold. These operations are performed with help of tanner tools at .18µm technology. The paper also discusses the low power design techniques for SRAM. There is a four type low power technique discussed here for SRAM. One is the Half-swing Pulse-mode techniques in which a Half-swing Pulse-mode gate family is used that in turn uses reduced input signal swing without sacrificing performance and saves the power. Second is a memory bank partitioning, in which memory array is partitioned to enhance the speed and to reduce the power. Third is the Quiet Bit line architecture in which the voltage of bit line stays as low as possible. To prevent the excessive full-swing charging on the bit line, one-side driving scheme for write operation is used and for read precharge free-pulling scheme is used to keep all bit lines at low voltages at all times. Fourth is the Pulsed Word line and Reduced Bit line Swing in which voltage at bit lines is reduced.

IJSRD, 2013

SRAMs), focusing on optimizing delay and power. As the scaling trends in the speed and power of SRAMs with size and technology and find that the SRAM delay scales as the logarithm of its size as long as the interconnect delay is negligible. Non-scaling of threshold mismatches with process scaling, causes the signal swings in the bitlines and data lines also not to scale, leading to an increase in the relative delay of an SRAM, across technology generations. Appropriate methods for reduction of power consumption were studied such as capacitance reduction, very low operating voltages, DC and AC current reduction and suppression of leakage currents to name a few.. Many of reviewed techniques are applicable to other applications such as ASICs, DSPs, etc. Battery and solar-cell operation requires an operating voltage environment in low voltage area. These conditions demand new design approaches and more sophisticated concepts to retain high device reliability. The proposed techniques (USRS and LPRS) are topology based and hence easier to implement.

With on growing technology scaling, low power operation has become important in VLSI design. SRAM consists large portion of the modern VLSI designs, thus efforts are being made to design low power SRAM using different ways. This paper discusses various existing SRAM designs, consisting of different number of transistors from one another. This paper focuses on the study of these designs and their comparison on the basis of parameters like power dissipation, access time , stability and power delay product. All the SRAM designs has different read write operation and hence different results. It was found that 12T SRAM has better performance in case of power dissipation and power dealy product but high access time than the other existing SRAM cells when compared on the basis of simulation results obtained on 45nm environment using Microwind tool.

The objective of this report is to describe the power consumption of a 7T-transistor SRAM cell. The basic operation and constraints of static RAM will be discussed, along with transistor sizing for device stability. The design will be covered using a symbolic schematic, as well as a physical device layout (both generated using Electric VLSI Design System). To demonstrate that this 6T SRAM cell design operates correctly for all four necessary functions: write HIGH, write LOW, read HIGH, and read LOW. The basic purpose of a memory cell is to hold a single bit of data, and this can be accomplished statically (without the need for refreshing) by using a pair of inverting gates. In order to read from and write to this invertor pair, access transistors are also needed.

With on growing technology scaling, low power operation has become important in VLSI design. SRAM consists large portion of the modern VLSI designs, thus efforts are being made to design low power SRAM using different ways. This paper discusses various existing SRAM designs, consisting of different number of transistors from one another. This paper focuses on the study of these designs and their comparison on the basis of parameters like power dissipation, access time , stability and power delay product. All the SRAM designs has different read write operation and hence different results. It was found that 12T SRAM has better performance in case of power dissipation and power dealy product but high access time than the other existing SRAM cells when compared on the basis of simulation results obtained on 45nm environment using Microwind tool.

2012

In the current technology demand for SRAM is increasing drastically due to its usage in almost all embedded systems, forms a integral part of computer, System On Chip and high performance processors and VLSI circuits etc. The Power Consumption has become a major concern in Very Large Scale Integration circuit designs and reducing the power dissipation has become challenge to the Low power VLSI designers. As power dissipation increases with the scaling of the technologies. As the feature size shrinks ,static power has become a great challenge for current and future technologies. In this research work, we design 6T SRAM and some of the techniques to reduce the leakage power using like sleep approach, stack approach techniques which reduces the leakage power without changing the exact operation of SRAM. The proposed circuits were designed in 0.18um CMOS VLSI technology with a Microwind tool, and measure the power dissipation for the different design approach in Advanced BSIM4 level. Po...

Memory is widely used in all electrical systems mainframes microcomputers and cellular phones etc. From the last more than five decades we are scaling down the size of the CMOS devices to make the devices portable and compact in size and to get better performance in terms of access time, power dissipation, delay etc. More memory means more information therefore more size and so more power consumption. Thus the demand for low size and low power memory has been raised. Working of low supply voltage and leakage energy has become main concern as the power consumption can be reduced significantly. We, in our work have designed the low power SRAM memory cells, which are used to store single bit information, under different configurations (6T, 8T, 9T) and compared various parameters of these cells. We have carried out the simulation work using Tanner SPICE. However, there is no universal way to avoid trade-offs between the power, delay and area. This is why; the designers are required to choose appropriate techniques that satisfy application and product needs.

International Journal of Engineering & Technology, 2018

In deep sub-micron technologies, high number of transistors is mounted onto a small chip area where, SRAM plays a vital role and is considered as a major part in many VLSI ICs because of its large density of storage and very less access time. Due to the demand of low power applications the design of low power and low voltage memory is a demanding task. In these memories majority of power dissipation depends on leakage power. This paper analyzes the basic 6T SRAM cell operation. Here two different leakage power reduction approaches are introduced to apply for basic 6T SRAM. The performance analysis of basic SRAM cell, SRAM cell using drowsy-cache approach and SRAM cell using clamping diode are designed at 130nm using Mentor Graphics IC Studio tool. The proposed SRAM cell using clamping diode proves to be a better power reduction technique in terms of power as compared with others SRAM structures. At 3.3V, power saving by the proposed SRAM cell is 20% less than associated to basic 6T ...

Over the years, the development of the logic on the chip is increased. To sustain and drive the logic flow, various techniques and SRAM cell designs have been implemented. The basic element of memory design is 6T SRAM cell. But while dealing with this 6T SRAM cell there are some issues with the parametric analysis on the performance of the cell. This paper presents an innovative design idea of new 8T RAM cell with various parametric analysis. The proposed cell is compared with the standard cell in terms of different parameters such as area, speed and power consumption along with the loading effect with the increase in load capacitance on the cell. The structure is designed with CMOS 45 nm Technology with BSIM 4 MOS modelling using Microwind 3.5 software tool.

as the size of ic's is becoming small, day by day the demand of high density vlsi circuits has been increasing .the supply voltage reduction is necessary to reduce the active power. By lowering the supply voltage it is effective ways to suppress the energy consumption because reducing the supply voltage could reduce the dynamic power and leakage power respectively. In this paper, a technique called cluster technique has been proposed to reduce the active power requirement and the simulation has been done on 8x1 sram cell. In this work firstly the power dissipation of all the cells are connected to an without sleep is taken out then sleep transistor shared with two cells and after that all the four cells are connected to only sleep. Leakage reduction techniques for cmos based transistor level design and the techniques have been proposed like leakage lector technique transistor stack based low leakage approach, sleeper keeper technique for leakage reduction, multiple threshold transistor design technique, gated-clock based low power design etc. Various proposed techniques provide benefits with respect to specific design application. Therefore, result with cluster technique improved result than an individual sleep when connected to the sram cell. In this paper, sram cell without sleep transistor dissipates more power during different states as compared to sram cell with an individual transistor.asthe conventional design is simulated on different cmos fabrication technology using microwind tool. I. INTRODUCTION As with every generation of technology, the demand of handling the large amount of data in embedded memory has been increasing. To fulfill the requirement handling large data feature size of transistor is continuously reducing. With respect to high transistor density the problem of power consumption is becoming prominent issue to tackle. Static Random Access Memory is the first choice of designing semiconductor embedded memories because of low power dissipation. The low power feature for on chip SRAMs is becoming more important especially for battery operated portable applications .It is however one of the most significant challenges of high density VLSI circuit .The main aim of this paper is to estimate the effect of clustering technique on 6T SRAM cell and to investigate transistor sizing of the 6T SRAM cell for optimum power and delay. In this work , an average power dissipation of 6T SRAM Cell has been compared with SRAM cell using cluster technique.The cluster technique reduces the power dissipation of 6T SRAM cell in read, write , and hold operation .

2006

Abstract: The explosive growth of battery operated devices has made low-power design a priority in recent years. Moreover, embedded SRAM units have become an important block in modern SoCs. The increasing number of transistor count in the SRAM units and the ...

International Journal of Innovative Technology and Exploring Engineering (IJITEE), 2019

The power consumption in commercial processors and application specific integrated circuits increases with decreasing technology nodes. Power saving techniques have become a first class design point for current and future VLSI systems. These systems employ large on-chip SRAM memories. Reducing memory leakage power while maintaining data integrity is a key criterion for modern day systems. Unfortunately, state of the art techniques like power-gating can only be applied to logic as these would destroy the contents of the memory if applied to a SRAM system. Fortunately, previous works have noted large temporal and spatial locality for data patterns in commerical processors as well as application specific ICs that work on images, audio and video data. This paper presents a novel column based Energy Compression technique that saves SRAM power by selectively turning off cells based on a data pattern. This technique is applied to study the power savings in application specific inegrated circuit SRAM memories and can also be applied for commercial processors. The paper also evaluates the effects of processing images before storage and data cluster patterns for optimizing power savings..

2018

Modern ICs are enormously complicated due to decrease in device size and increase in chip density involving several millions of transistors per chip. The rules for what can and cannot be manufactured leads to a tremendous increase in complexity due to the amount of power dissipation are increased. For high-speed memory applications such as cache, a SRAM is often used. Power consumption is the key parameter for an SRAM memory design (SRAM). In this paper an effort is made to design 6T, 7T, 8T, 9T, 10T, 11T SRAM cells using Cadence 180nm technology. The average power consumption of these SRAM cells are calculated and compared.