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The results of a genetic algorithm optimisation of the scheduling and allocation phases of high-level synthesis are reported. Scheduling and allocation are NP complete, multi-objective phases of high-level synthesis. A high-level synthesis system must combine the two problems to produce optimal results. The genetic algorithm described provides a robust and efficient method of search capable o] combining scheduling and allocation phases, and responding to the multiple and changing objectives of high-level synthesis. The results show the genetic algorithm succeeds in finding optimal or near optimal results to classic benchmarks in small computational time spans. 1 I n t r o d u c t i o n High-level synthesis (HLS) is the automated synthesis of a register transfer level circuit from a behavioural description, summarised in [W94]. A behavioural circuit description specifies the ultimate goals of the circuit in terms of its logical function, timing and chip area constraints. High-level synthesis systems use the behavioural description to generate a structural design implementing a specified behaviour. The structural design consists of functional units such as arithmetic logic units (ALUs), multipliers, registers and buses. High-Level Synthesis involves two NP Complete optimisations. The first is a problem of scheduling in which the operations given by the behavioural description are assigned a control step. The second, which may be performed before, after or simultaneously to scheduling, is allocation, which assigns functional units to operations given in the behavioural description. These two optimisation phases have multiple minimisation objectives; i.e. to minimise functional units, control steps needed by the circuit, registers needed to store values, and the number of buses to interconnect the circuit. It is not possible to minimise all objectives; the desired goals for the circuit must be considered by the optimisation process for the optimisation of all objectives. Previous solutions to the problem have failed to adapt well to changing objectives.
2000
This paper describes a genetic algorithm applied to high-level hardware synthesis, generating a register transfer level circuit from a behavioral speci cation of a hardware system. High-Level synthesis consists of two combinatorial optimization problems; scheduling and allocation. It is also a multiple objective problem. Our GA solves the scheduling and allocation problems simultaneously so that it can successfully avoid falling into local minimums and cope with multiple objectives, giving di erent weight to tness functions. Several new ideas are involved in our paper. One is a straightforward method obtaining o spring e ciently using GA operations with a mechanism repairing faulty genes when creating o spring. E cient creation is crucial to an optimization problem with severe restrictions since most o spring violate the environment. When a gene violates the environment, it is replaced by the alternative parent gene or one of the available genes in order to repair the violating gene. Another idea is to di erentiate the circuits with the same tness to the environment from the viewpoint of closeness to the assumed optimal circuit. This di erentiation can strongly avoid premature convergence, wandering around a better solution through many generations. Using these ideas, our GA has succeeded in obtaining improved solutions, compared to other high level synthesis optimization techniques,for bench mark problems.
2007
In this paper we present the application of our ATPGbased design rewiring approach to multi-level combinational logic circuit optimization. At every step of this optimization procedure, we introduce a design error by removing the logic that violates the optimization constraint(s) and then we attempt to correct the design by modifying the logic somewhere else. We give heuristics and describe the application of this method to delay optimization and to design for low power. Experiments are also presented to support the potential of our method. Ivor Ting Andreas Veneris Magdy S. Abadir Alcatel University of Toronto Motorola 4190 Still Creek Drive Dept ECE and CS 7700 W. Parmer Burnaby, BC V5C 6C6 Toronto, ON M5S 3G4 Austin, TX 78729 [email protected] [email protected] [email protected]
Proceedings of 9th International Conference on VLSI Design
Microprocessors and Microsystems, 2002
In this paper, we present a new evolutionary algorithm, developed for scheduling and allocating in the automatic integrated circuit synthesis. It involves the scheduling of the operations and resource allocation for logic circuit design, with the object of speeding up the whole design process. The ®rst part of the paper presents the design optimization algorithm and its main functions, while in the second part the algorithm is compared with some other scheduling algorithms. The evaluation with cost factors, relating execution time and resource utilization, is made through different benchmark examples and various scheduling algorithms. We found that this evolutionary approach made the best or at least promising solutions in all tests and is therefore very appropriate for use in the automatic circuit design. q
2010
Recently, it has been shown that synthesis of some circuits is quite difficult for conventional methods. In this paper we present a method of minimization of multi-level logic networks which can solve these difficult circuit instances. The synthesis problem is transformed on the search problem. A search algorithm called Cartesian genetic programming (CGP) is applied to synthesize various difficult circuits. Conventional circuit synthesis usually fails for these difficult circuits; specific synthesis processes must be employed to obtain satisfactory results. We have found that CGP is able to implicitly discover new efficient circuit structures. Thus, it is able to optimize circuits universally, regardless their structure. The circuit optimization by CGP has been found especially efficient when applied to circuits already optimized by a conventional synthesis. The total runtime is reduced, while the result quality is improved further more.
2004 IEEE International Symposium on Circuits and Systems (IEEE Cat. No.04CH37512), 2004
This paper presents a time-constrained synthesis scheme to minimize power consumption with resources operating at multiple voltages. The input to our scheme is an unscheduled data flow graph, and the timing constraints. The proposed scheme, with polynomial time complexity, has following four steps. 1) The initial resource running at the lowest possible voltage is selected for each operation from a design library. 2) Operations are then scheduled with the objectives to minimize the power consumption due to the resources. 3) Operations are clustered to form voltage islands to minimize the power consumption due to the interconnections. Note that in both Steps 2 and 3, some operations may have to be reassigned to the resources to satisfy the timing constraints and reduce the interconnections, respectively. 4) Operations are finally bound to the resources. Experiments with a number of DSP benchmarks show that the proposed algorithms achieve the power reduction by an average of 46.5%.
IEEE Transactions on Evolutionary Computation, 2001
This paper presents a new tool for the synthesis of low-power VLSI designs, specifically, those designs targeting digital signal processing applications. The synthesis tool genetic algorithm for low-power synthesis (GALOPS) uses a genetic algorithm to apply power-reducing transformations to high-level signal-processing designs, producing designs that satisfy power requirements as well as timing and area constraints. GALOPS uses problem-specific genetic operators that are specifically tailored to incorporate VLSI-based digital signal processing design knowledge. A number of signal-processing benchmarks are used to facilitate the analysis of low-power design tools, and to aid in the comparison of results. Results demonstrate that GALOPS achieves significant power reductions in the presented benchmark designs. In addition, GA-LOPS produces a family of unique solutions for each design, all of which satisfy the multiple design objectives, providing flexibility to the VLSI designer.
IEEE Transactions on Computer-aided Design of Integrated Circuits and Systems, 1993
A relaxed LP model, which simultaneously schedules and allocates functional units and registers, is presented for synthesizing cost-constrained globally optimal architectures. This research is important for industry by providing exploration of optimal synthesized architectures since it is well known that early architectural decisions have the greatest impact on the final design. A mathematical integer programming formulation of the architectural synthesis problem was transformed into the node packing problem. Polyhedral theory was used to formulate constraints that decreased the size of the search space, thus improving integer programming solution efficiency. Execution times are an order-of-magnitude faster than previous research that uses heuristic techniques. This research breaks new ground by 1) simultaneously scheduling and allocating in practical execution times, 2) guaranteeing globally optimal solutions for a specific objective function, and 3) providing a polynomial run-time algorithm for solving some instances of this NP-complete problem.
2008
The complexity of the digital electronic circuit is due to the number of gates used per system as well as the interconnection of the gates. Diminution of the total number of gates used and interconnection in the system would reduce the cost in the design, as well as increasing the efficiency of the overall system. As a result, the higher integration level, the better and the cheaper final product produced. The conventional digital circuit design method is based on Boolean algebra. There are no specific procedure to choose the right theorem or postulate for the Boolean expression simplification and it is very impractical to design the digital circuits that have more than four variable. Karnaugh map can provide the simple minimization process for Boolean expression, but it encounters difficulties when the variable is more than four. 129 4.11 The Design 3-1 Successful Chromosome Bits on GALI 130 4.12 The K-Map Solution for Design 3-1 130 4.13 4-bit Digital Circuit Structure 135 4.14 The Control Panel of the 4-Bit ODCSD 137 4.15 The Simulation Result for Design 4-1 138 4.16 The Constraint Fitness for Design 4-1 139 4.17 The Design 4-1 Successful Chromosome Set on GALI 140 4.18 Design 4-1 Successful Chromosome Bits on GALI 142 4.19 The K-Map Solution for Design 4-1 142 4.20 5-Bit Digital Circuit Structure 142 4.21 The Control Panel of the 5-Bit ODCSD 150 4.22 The Simulation Result for Design 5-1 151 4.23 The Constraint Fitness for Design 5-1 151 xix 4.24 The Design 5-1 Successful Chromosome Set on GALI 152 4.25 Design 5-1 Successful Chromosome Bits on GALI 154 4.26 Design 5-1 by using Karnaugh Minimizer 155 4.27 6-Bit Digital Circuit Structure 158 4.28 The Control Panel of the 6-Bit ODCSD 159 4.29 The Simulation Result for Design 6-1 160 4.30 The Constraint Fitness for Design 6-1 161 4.31 he Design 6-1 Successful Chromosome Set on GALI 162 4.32 Design 6-1 Successful Chromosome Bits on GALI 165 4.33 Design 6-1 by using Karnaugh Minimizer 166 4.34 The Simulation Result for the first Circuit Designed by Mentor Graphics 172 4.35 The Simulation Result for the second Circuit Designed by Mentor Graphics 173 4.36 The Simulation Result for the first Circuit Designed by Quine McCluskey 176 4.37 The Simulation Result for the second Circuit Designed by Quine McCluskey
2005
Early scheduling algorithms usually adjusted the clock cycle duration to the execution time of the slowest operation. This resulted in large slack times wasted in those cycles executing faster operations. To reduce the wasted times multi-cycle and chaining techniques have been employed. While these techniques have produced successful designs, its effectiveness is often limited due to the area increment that may derive from chaining, and the extra latencies that may derive from multicycling. In this paper we present an optimization method that solves the time-constrained scheduling problem by transforming behavioural specifications into new ones whose subsequent synthesis substantially improves circuit performance. Our proposal breaks up some of the specification operations, allowing their execution during several possibly unconsecutive cycles, and also the calculation of several data-dependent operation fragments in the same cycle. To do so, it takes into account the circuit latency and the execution time of every specification operation. The experimental results carried out show that circuits obtained from the optimized specification are on average 60% faster than those synthesized from the original specification, with only slight increments in the circuit area.
Proceedings of the Design Automation & Test in Europe Conference, 2006
Conventional high-level synthesis uses the worst case delay to relate all inputs to all outputs of an operation. This is a very conservative approximation of reality, especially in arithmetic operations (where some bits are required later than others and some bits are produced earlier than others). This paper proposes a pre-synthesis optimization algorithm that takes advantage of this feature for more efficient high-level synthesis of data-flow graphs formed by additions and multiplications. The presented pre-processor analyzes the critical path at bitgranularity and splits the arithmetic operations into subwords fragments. In particular, some of the specification multiplications are broken up into several smaller multiplications, additions, and other operations of three new types specially defined to reduce the clock cycle duration. These fragments become the input to any regular high-level synthesis tool to speed up circuit execution times. The experimental results carried out show that implementations obtained from the optimized specification are on average 70% faster and in most cases substantial area reductions are also achieved.
International Journal of Engineering Research and, 2017
In this paper we illustrate the retiming technique to reduce the iteration period and to minimize the registers. So by this technique computation time is reduced for processors and fast speed is achieved. This is used in real time implementation to optimize performance. Shortest path algorithm such as Bellman ford and Floyd Warshall are used in retiming. These retiming techniques are explained in quantitative manner and the results are given thereafter. Retiming helps in reducing switching time. Minimization of the registers through retiming can help in reducing memory requirement and also reduce the requirement of area. And thereafter power consumption is also reduced due to less area and less switching time as given by the equation of dynamic power.
2019
Background and Objectives: High-level synthesis (HLS) is one of the substantial steps in designing VLSI digital circuits. The primary purpose of HLS is to minimize the digital units used in the system to improve their power, delay, and area. Methods: In the modified MFO algorithm presented in this paper, a hyperbolic spiral is chosen as the update mechanism of moths. Also, by presenting a new approach, a paramount issue involved in applying metaheuristic methods for solving HLS problems of VLSI circuits has been disentangled. Results: By comparing the performance of the proposed method with Genetic algorithm (GA)-based method and particle swarm optimization (PSO)-based method for the synthesis of the digital filters, it is concluded that the proposed method has the higher ability in the HLS of data path in digital filters. The best improvement is 2.78% for the delay (latency), 6.51% for the occupied area of the chip and 6.93% in power consumption. Another feature of the proposed method is its high-speed in finding optimal solutions, in a manner which, more than 21.6% and 12.9% faster than the GA-based and PSO-based methods, respectively on average. Conclusion: The most important very large scale integration (VLSI) circuits are digital filters and transformers, which are widely used in audio and video processing, medical signal processing, and telecommunication systems. The complex, expansive, and discrete nature of design space in high-level synthesis problems has made them one of the most difficult problems in VLSI circuit design.
Proceedings of the 1995 international symposium on Low power design - ISLPED '95, 1995
Decisions taken at the earliest steps of the design process may have a significant impact on the characteristics of the final implementation. This paper illustrates how power consumption issues can be tackled during high-level synthesis (high-level transformations, scheduling and binding). Several techniques pursuing low power are proposed and the potential benefits evaluated. The common idea behind these techniques is to reduce the activity of the functional units (e.g. adders, multipliers) by minimizing the changes of their input operands. Preliminary evaluations obtained from switch-level simulations show that significant improvements can be achieved.
Proceedings. The Second NASA/DoD Workshop on Evolvable Hardware, 2000
This paper introduces a new methodology of evolving electronic circuits by which the process of evolutionary design is guaranteed to produce a functionally correct solution. The method employs a mapping to represent an electronic circuit on an array of logic cells that is further encoded within a genotype. The mapping is many-to-one and thus there are many genotypes that have equal fitness values. Genotypes with equal fitness values define subgraphs in the resulting fitness landscapes referred to as neutral networks. This is further used in the design of a neutral network that connects the conventional with other more efficient designs. To explore such a network a navigation strategy is defined by which the space of all functionally correct circuits can be explored. The paper shows that very efficient digital circuits can be obtained by evolving from the conventional designs. Results for several binary multiplier circuits such as the three and four-bit multipliers are reported. The evolved solution for the three-bit multiplier consists of ¡ two-input logic gates that in terms of number of two-input gates used is ¡ ¢¡ £ more efficient than the most efficient known conventional design. The logic operators required to implement this circuit are ¤ ¥ ANDs, ¦ XORs, and inversions (NOT). The evolved four-bit multiplier consists of § two-input logic gates that is ¤ © ¢ ¦ £ more efficient (in terms of number of two-input gates used) than the most efficient known conventional design. The optimal size of the target circuits is also studied by measuring the length of the neutral walks from the obtained designs.
International Journal of Circuits and Architecture Design, 2013
This paper presents a comprehensive comparison between Levenberg-Marquardt (LM) and logical effort (LE) theory-based optimisation techniques. While LM is a classical approach for optimisation and is embedded in SPICE, logical effort-based approach is contemporary, design specific and needs simple back of the envelope calculations for optimisation of digital circuits. Both the approaches have been used by digital circuit designers in the literature for comparing a proposed digital circuit with the existing designs while optimising any given design for timing, power and area parameters. The goal of writing this paper is to make digital system designers gain an insight into the procedures used for optimising digital circuits while at the same time a well-defined approach using LM algorithm is provided that can be easily automated with the current generation CAD tools. For the purpose of comparison some standard circuits were chosen and optimised for minimum PDP and PDAP. SPICE simulations have been extensively used for comparing the two methodologies in a 180 nm\1.8 V CMOS technology.
8th International Symposium on Quality Electronic Design (ISQED'07), 2007
This paper studies multi-dimensional optimization at both circuit and micro-architecture levels. By formulating and solving the optimization problem with conflicting design objectives and multiple tunable knobs, it is revealed that the 'sensitivity balance' strategy proposed in recent works for performance-energy optimization is a special case of a general multi-dimensional optimization framework. The results derived in this paper help the understanding of efficient trade-off among multiple design objectives with multiple knobs. The example of an industrial control logic implemented in PLA shows 22% energy saving and 70% area reduction at the expense of 4% delay increase.
IEEE Journal of Solid-state Circuits, 1992
An integer programming (IP) model, which simultaneously schedules and allocates functional units, registers, and buses, is presented for synthesizing cost-contrained globally optimal architectures. This research is important for industry by providing optimal schedules that minimize interconnect costs and interface to analog and asynchronous processes, since these are seen as key to synthesizing high-performance architectures. A mathematical IP model of the architectural synthesis problem is formulated. A subset of the constraints is transformed into the node-packing problem and integral facets are extracted and generalized. Other constraints are tightened or mapped into the knapsack problem and facets are extracted and generalized. Area-delay cost functions are minimized using branch and bound on the resulting IP model. Globally optimal architectures are synthesized in faster CPU times than previous research. This research breaks new ground by: 1) providing industry with interconnect-optimized architectures since interconnect is seen as the key to high performance; 2) synthesizing globally optimal architectures in faster execution times than current heuristic techniques; 3) supporting interfaces to asynchronous and analog interfaces; and 4) supporting piecewise linear area-delay cost functions.
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