Constraint-driven system partitioning

Co-design methodology deals with the problem of designing complex embedded systems, where Hardware/software partitioning is one key challenge. It decides strategically the system's tasks that will be executed on general purpose units and the ones implemented on dedicated hardware units, based on a set of constraints. Many relevant studies and contributions about the automation techniques of the partitioning step exist. In this work, we explore the concept of the hardware/software partitioning process. We also provide an overview about the historical achievements and highlight the future research directions of this co-design process.

ACM Transactions on Design Automation of Electronic Systems, 2003

This paper presents an in-depth study of several system partitioning procedures. It is based on the appropriate formulation of a general system model, being therefore independent of either the particular co-design problem or the specific partitioning procedure. The techniques under study are a knowledge-based system and three classical circuit partitioning algorithms (Simulated Annealing, Kernighan&Lin and Hierarchical Clustering). The former has been entirely proposed by the authors in previous works while the later have been properly extended to deal with system level issues. We will show how the way the problem is solved biases the results obtained, regarding both quality and convergence rate. Consequently it is extremely important to choose the most suitable technique for the particular co-design problem that is being confronted.

1997

This paper presents the underlying methodology of Cosmos, an interactive approach for hardware software c o-design capable of handling multiprocessor systems and distributed a r chitectures. The approach covers the co-design process through a set of user guided t r ansformations allowing semi-automatic partitioning. The transformations are b ased o n a p owerful set of primitives for functional partitioning, structural reorganization and communication transformation. It leads to a fast transformation of a systemlevel speci cation into an architecture with a short design time and fast exploration of design space. The application of this approach is illustrated using a design example starting from a system-level speci cation given in SDL to a distributed hardware software a r chitecture described in C VHDL. We show that the use of transformational approach allows:

ACM Transactions on Design Automation of Electronic Systems, 2003

This paper presents an in-depth study of several system partitioning procedures. It is based on the appropriate formulation of a general system model, being therefore independent of either the particular co-design problem or the specific partitioning procedure. The techniques under study are a knowledge-based system and three classical circuit partitioning algorithms (Simulated Annealing, Kernighan&Lin and Hierarchical Clustering). The former has been entirely proposed by the authors in previous works while the later have been properly extended to deal with system level issues. We will show how the way the problem is solved biases the results obtained, regarding both quality and convergence rate. Consequently it is extremely important to choose the most suitable technique for the particular co-design problem that is being confronted.

Proceedings International Conference on Computer Design. VLSI in Computers and Processors (Cat. No.98CB36273)

Partitioning is a very important task in hardware/software co-design. Generally the size of the edge cut-set is used to evaluate the communication cost. When communication between components is through buffered channels, the size of the edge cut-set is not adequate to estimate the buffer size. A second important factor to measure the quality of partitioning is the system delay. Most partitioning approaches use the number of nodes/functions in each partition as constraints and attempt to minimize the communication cost. The data dependencies among nodes/functions, and their delays are not considered. In this paper we present partitioning with two objectives: (1) buffer size, which is estimated by analyzing the data flow patterns of the CDFG, and solved as a clique partitioning problem, and (2) the system delay that is estimated using List Scheduling. We pose the problem as a combinatorial optimization and use an efficient non-deterministic search algorithm called Problem-Space Genetic Algorithm to search for the optimum. Results are compared with those produced by simulated annealing.

International Journal of Advanced Intelligence Paradigms, 2019

Embedded systems have a wide range as they have become essential parts of modern life. A typical embedded system consists of application-specific hardware and programmable software. Hardware-software (HW/SW) partitioning problem defines which tasks should be mapped to software and hardware. It allows the proposition of an optimised system with predefined constraints. In this paper, a heuristic algorithm, the hybrid-bee-colony-optimisation for multiple-choice HW/SW partitioning is proposed. The proposed algorithm aims to minimise power consumption and execution time, while meeting area constraint. This heuristic algorithm is developed to generate an approximate solution in acceptable delay. The Virtex 5 is chosen as a target platform. Simulation results are compared with existing works and they show rapidity with the generation of an optimal solution near to the exact one.

2015

This paper presents a comparative study between two algorithms of hardware/software partitioning which aim to minimize the logic area of System on a Programmable Chip (SOPC) while respecting a time constraint. The first algorithm is based on the genetic algorithm (AG), the second one is our proposed algorithm which is based on the principle of Binary Search Trees (BST) and genetic algorithms (AG). The two algorithms aim to define the tasks that will run on the Hardware (HW) part and those that will run on the Software (SW) part. They seek to find the efficient hardware/software partition that minimize the number of tasks used by the HW and increase the number of tasks used by the SW, in order to balance all the design parameters and have a better trade-off between the logic area of the application and its execution time.

Electronic Notes in Theoretical Computer Science, 2006

Program slicing is a software analysis technique and generates System Dependence Graphs (SDGs) by which dependences among program statements can be identified. In this paper, we propose a new hardware-software co-design methodology based on the static and partially dynamic dependence analysis with SDG. We start with any combinations of C, C++, and SpecC descriptions so that flexible functional specifications of the HW/SW systems can be made. First of all, the input descriptions are analyzed and verified with the SDG generated from the input descriptions. Actual analyses and verifications are based on static ones but partially with dynamic ones as well, and fairly large descriptions can be processed. After these analyses, we divide the system into hardware and software parts by optimizing the design descriptions and introducing parallelism if necessary. In this HW/SW partitioning, SDG generated from C / C++ / SpecC design descriptions is fully utilized to extract / convert / pack the HW parts from the entire descriptions. This flexibility of HW/SW partitioning is one of the main differences from previous HW/SW partitioning methods. The extracted HW parts are further optimized and then converted into RTL descriptions by existing behavioral synthesis tools. As the last step, the generated RTL descriptions together with SW parts are compared to the original descriptions in order to make sure that they are logically equivalent. Also, designer-specified properties may be model checked with these final design descriptions. These equivalence checking and model checking can be realized by first translating the HW/SW design descriptions into FSM type representations. The translated FSM type representations are further processed by existing formal verifiers. We present the proposed HW/SW co-design methodology with an illustrating example as well as actual application to real designs and demonstrate the usefulness of our approach.

2000

Abstract Current software and hardware co-synthesis methodologies of control dominated embedded systems focus primarily on improving productivity in the complex design process. In order to improve synthesis quality, we propose a methodology that incorporates data flow and control optimizations performed on a novel implementation independent design task representation. The approach is applicable to any co-synthesis tool; we use a public domain co-design environment to report some results of our investigation.

Design Automation for Embedded Systems, 2011

Embedded systems are widely used in many sophisticated applications. To speed the time-to-market cycle, the hardware and software co-design has become one of the main methodologies in modern embedded systems. The most important challenge in the embedded system design is partitioning; i.e. deciding which modules of the system should be implemented in hardware and which ones in software. Finding an optimal partition is hard because of the large number and different characteristics of the modules that have to be considered.