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Digital Signal Processing

Abstract

Lecture – 29 IIR Realizations This is the 29 th lecture on DSP and our topic today is IIR Realizations. In the previous lecture, we talked about the process of transposition and then FIR realization. We discussed the direct form structure, its transposed structure, the cascade structure and the parallel structure. The parallel is obtained by polyphase decomposition and parallel in FIR does not lead to a higher speed. Even if it is parallel processing, the speed cannot be increased but the realization can be made canonic by sharing delays. We took an example to illustrate this. Polyphase decomposition is not normally resorted to because it does not speed up processing, but it is very useful in multi rate signal processing where decimation and interpolation do reduce the computational complexity. Then we said that in the linear phase realizations, because of symmetry or anti-symmetry, the number of multipliers can be reduced approximately a factor of half, exactly half if the length is even or order length + 1 divided by 2 if the order is odd. Today we will discuss about IIR Realizations.

Key takeaways

  • So the FIR would be in parallel with IIR realization and that would speed up the process.
  • For the particular problem of a 4 th degree numerator and 3 rd degree denominator, if you realize by 1 st order FIR in parallel with 3 rd order IIR, the first output sample would be available after 3 delays, not 4.
  • This is the case if N is even; on the other hand if N is odd then in addition to this you add a bilinear function of the form (1 + d 1 We can also have parallel realization, which now assumes importance.
  • In parallel realization, you require factorizing the denominator only, whereas in cascade you require factorizing the denominator as well as the numerator because you have to assign numerator factors to second order transfer functions and to the first order transfer functions, if the overall order is odd.
  • All pass IIR has the problem that the direct or cascade or parallel realization cannot be made canonic in multipliers.