Reversible logic synthesis by iterative compositions

2000

Reversible circuits are currently on of top approaches to power minimization and the one whose importance will be only growing with time. In this paper, the well known Feynman gate is generalized to k*k gate and a new generalized k*k family of reversible gates is proposed. A synthesis method for multi-output SOP function using cascades of the new gate family

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2006

Reversible logic finds many applications, especially in the area of quantum computing. A completely specified n-input, n-output Boolean function is called reversible if it maps each input assignment to a unique output assignment and vice versa. Logic synthesis for reversible functions differs substantially from traditional logic synthesis and is currently an active area of research. The authors present an algorithm and tool for the synthesis of reversible functions. The algorithm uses the positive-polarity Reed-Muller expansion of a reversible function to synthesize the function as a network of Toffoli gates. At each stage, candidate factors, which represent subexpressions common between the Reed-Muller expansions of multiple outputs, are explored in the order of their attractiveness. The algorithm utilizes a prioritybased search tree, and heuristics are used to rapidly prune the search space. The synthesis algorithm currently targets the generalized n-bit Toffoli gate library. However, other algorithms exist that can convert an n-bit Toffoli gate into a cascade of smaller Toffoli gates. Experimental results indicate that the authors' algorithm quickly synthesizes circuits when tested on the set of all reversible functions of three variables. Furthermore, it is able to quickly synthesize all four-variable and most five-variable reversible functions that were in the test suite. The authors also present results for some benchmark functions widely discussed in literature and some new benchmarks that the authors have developed. The algorithm is shown to synthesize many, but not all, randomly generated reversible functions of as many as 16 variables with a maximum gate count of 25.

Arxiv preprint arXiv:0710.0664, 2007

Reversible logic [4, 11] is one of the hot areas of research. It has many applications in quantum computation [13, 23], low-power CMOS [8, 31] and many more. Synthesis and optimization of reversible circuits cannot be done using conventional ways [29]. The design and analysis ...

Design, Automation, and Test in Europe, 2004

A function is reversible if each input vector produces a unique output vector. Reversible functions find applications in low power design, quantum computing, and nanotechnology. Logic synthesis for reversible circuits differs substantially from traditional logic synthesis. In this paper, we present the .rst practical synthesis algorithm and tool for reversible functions with a large number of inputs. It uses positive-polarity

Proceedings of the great …, 2012

Reversible computing dissipates zero energy in terms of information loss at input and also it can detect error of circuit by keeping unique input-output mapping. In this paper, we have proposed a cost effective design of Reversible Programmable Logic Arrays (RPLAs) which is able to realize multi-output ESOP (Exclusive-OR Sum-Of-Product) functions by using a cost effective 3×3 reversible gate, called MG (MUX Gate). Also a new algorithm has been proposed for the calculation of critical path delay of reversible PLAs. The minimization processes consist of algorithms for ordering of output functions followed by the ordering of products. Five lower bounds on the numbers of gates, garbages and quantum costs of reversible PLAs are also proposed. Finally, we have compared the efficiency of proposed design with the existing one by providing benchmark functions analysis. The experimental results show that the proposed design outperforms the existing one in terms of numbers of gates, garbages, quantum costs and delay.

IEEE Transactions on …, 2003

Reversible logic circuits have been historically motivated by theoretical research in low-power electronics as well as practical improvement of bit-manipulation transforms in cryptography and computer graphics. Recently, reversible circuits have attracted interest as components of quantum algorithms, as well as in photonic and nano-computing technologies where some switching devices offer no signal gain. Research in generating reversible logic distinguishes between circuit synthesis, post-synthesis optimization, and technology mapping. In this survey, we review algorithmic paradigms -search-based, cycle-based, transformationbased, and BDD-based -as well as specific algorithms for reversible synthesis, both exact and heuristic. We conclude the survey by outlining key open challenges in synthesis of reversible and quantum logic, as well as most common misconceptions.

2004

In the recent years, reversible logic has emerged as a promising technology having its applications in low power CMOS, quantum computing, nanotechnology, and optical computing. A reversible circuit maps each output vector into a unique input vector, and vice versa. There always has been a hurdle in realization and optimization of reversible circuit. One way of realizing reversible logic is quantum computers. Quantum computing has been a field of growing interest in the last decade because of its promises to reduce power consumption. This paper presents realization of reversible circuits such as adder and multiplier using three different methods which are as follows CMOS logic, Quantum cellular automata (QCA), and jQuantum. Although CMOS don’t take full benefit of reversibility criteria but it is used for functional verification of reversible circuit design. In this paper we have implemented few reversible circuits in CMOS and their layout is presented. QCA is a new technology for realization of quantum circuits. Minimum area full adder has been implemented in QCAD and presented in this paper. This paper also proposes a design of a reversible multiplier with minimum complexity in terms of gates. This multiplier design has been verified using jQuantum which is a JAVA simulator which designs reversible circuits based on quantum wires. A novel design of a 4x4 multiplier has also been proposed. Thus, this paper proposes different methods for realising reversible logic and their optimization techniques.

ACM Computing Surveys, 2013

Reversible logic circuits have been historically motivated by theoretical research in low-power electronics as well as practical improvement of bit-manipulation transforms in cryptography and computer graphics. Recently, reversible circuits have attracted interest as components of quantum algorithms, as well as in photonic and nano-computing technologies where some switching devices offer no signal gain. Research in generating reversible logic distinguishes between circuit synthesis, post-synthesis optimization, and technology mapping. In this survey, we review algorithmic paradigms-search-based, cycle-based, transformationbased, and BDD-based-as well as specific algorithms for reversible synthesis, both exact and heuristic. We conclude the survey by outlining key open challenges in synthesis of reversible and quantum logic, as well as most common misconceptions. 1 While charge recovery reminds conservative logic [Fredkin and Toffoli 1982], its essential property is to avoid dissipating electric charges by exchanging them. This property requires transistor-level support and is not specific to logic circuits as it also applies to clock networks.