Parallel system

Computer Physics Communications, 1985

The MIMD approach is a realistic and cost-effective means to increase computer performance, avoiding major inefficiencies of current pipelined supercomputers. We are studying several MIMD computer organizations and a control language allowing parallel programming. Firstly, we briefly present our language characteristics and capabilities: in our approach, a program can be viewed as a collection of computational tasks, together with a sequencing task, which expresses dependences among them and thus shows concurrency and synchronization. In order to illustrate the programming methodology in our MIMD environment, we consider a program, called PASFR, taken from actual applications in numerical areas (finite difference method). In this paper, our concern is to examine several possible descriptions of the same program, in terms of algorithmic tasks, and the corresponding expression of the flow of control between them. In other words, we present different decomposition schemes of this application into concurrent tasks, which essentially depend on the size of the elementary tasks. We then compare the behaviour of each version, in terms of effective performance, running each one on our architecture simulator. Finally, we propose some optimization strategies for speed enhancement, based on data-transfer improvement.

Computer Physics Communications, 1982

The need to run large, compute-bound programs encountered in research, coupled with the high availability of mini-and microcomputers in the laboratory environment, has prompted the linking of independent processors to form multicomputer systems. Important characteristics of the system presented here are the lack of shared memory between processors and the use of purely standard hardware to effect the linking. The resulting MIMD machine is suitable for executing asynchronous and weakly synchronous parallel programs. This is facilitated by assembly language software support to handle communication and to organise the independent sections of executable code for the individual processors. The design principles involved in this hardware configuration and the attendant software are introduced. A brief description of program execution behaviour is given. Applications and examples of programming problems which have been implemented on the system are discussed. An empirical method for assessing the timewise gain which ensues from use of the system is presented and experimental results obtained are outlined.

Citeseer

his paper presents a technique that may be used to transform SIMD shared memory parallel s algorithms to MIMD distributed memory algorithms. This technique formulates a sequence of teps to help alter the the global view required of the programmer for SIMD processing to the d more local one necessary for MIMD programming. Exercises based on this technique aid stu ents in understanding the fundamental differences between the two types of architectures.

Parallelism at level of instruction..

2016 49th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO), 2016

In the single-instruction multiple-threads (SIMT) execution model, small groups of scalar threads operate in lockstep. Within each group, current SIMT hardware implementations serialize the execution of threads that follow different paths, and to ensure efficiency, revert to lockstep execution as soon as possible. These constraints must be considered when adapting algorithms that employ synchronization. A deadlockfree program on a multiple-instruction multiple-data (MIMD) architecture may deadlock on a SIMT machine. To avoid this, programmers need to restructure control flow with SIMT scheduling constraints in mind. This requires programmers to be familiar with the underlying SIMT hardware. In this paper, we propose a static analysis technique that detects SIMT deadlocks by inspecting the application control flow graph (CFG). We further propose a CFG transformation that avoids SIMT deadlocks when synchronization is local to a function. Both the analysis and the transformation algorithms are implemented as LLVM compiler passes. Finally, we propose an adaptive hardware reconvergence mechanism that supports MIMD synchronization without changing the application CFG, but which can leverage our compiler analysis to gain efficiency. The static detection has a false detection rate of only 4%-5%. The automated transformation has an average performance overhead of 8.2%-10.9% compared to manual transformation. Our hardware approach performs on par with the compiler transformation, however, it avoids synchronization scope limitations, static instruction and register overheads, and debuggability challenges that are present in the compiler only solution. 1 We use the term "MIMD machine" to mean any architecture that guarantees loose fairness in thread scheduling so that threads not waiting on a programmer synchronization condition make forward progress.

Characteristics of multiprocessors  A multiprocessor system is an interconnection of two or more CPUs with memory and input-output equipment.  The term "processor" in multiprocessor can mean either a central processing unit (CPU) or an input-output processor (IOP).  Multiprocessors are classified as multiple instruction stream, multiple data stream (MIMD) systems  The similarity and distinction between multiprocessor and multicomputer are o Similarity  Both support concurrent operations o Distinction  The network consists of several autonomous computers that may or may not communicate with each other.  A multiprocessor system is controlled by one operating system that provides interaction between processors and all the components of the system cooperate in the solution of a problem.  Multiprocessing improves the reliability of the system.  The benefit derived from a multiprocessor organization is an improved system performance.

1999

A new concept of parallel architecture for image processing is presented in this paper. Named LAPMAM (Linear array processors with Multi-mode Access Memory), this architecture, for a 512 x 512 image, has 512 processors and four memory planes each of 512² memory modules. One important characteristic of this architecture is its memories modules that allow different access modes: RAM, FIFO, normal CAM and interactive CAM. This particular memory and a linear structure of RISC processors are combined with a tree interconnection network to obtain very efficient 1-d architecture suitable for real time image processing. The processor works in SIMD mode and allows a restricted MIMD mode without requiring a great hardware complexity. A hardware simulation of an architecture prototype has been accomplished to test its performance in low and intermediate level vision tasks. The performance of the LAPMAM is compared with that of different architectures.

Fourth IEEE Region 10 International Conference TENCON, 1989

In this paper, we describe a software environment for general purpose MIMD machines based on packet switched message passing paradigms. The environment provides system calls for communication between various processing elements in the machine and system calls to get the configuration of the system. It assumes the presence of a Host processor through which facilities are provided for forking remote processes on various processing elements. The Host processor has all peripherals of the system and acts as an I/O processor of the system. During normal course of execution, it forks processes, collects results from various processing elements, sequences them. and then produces output of the program.

The Mermaid project focuses on the construction of simulation models for MIMD multi-computers in order to evaluate them and to give estimates of the system's performance. A multi-layered approach was adopted in which three levels can be distinguished. The application level describes application behaviour in an abstract manner, unrelated to any hardware or architecture specifics. Subsequently, the generation level translates these application descriptions to a hardware dependent trace of operations that drives the simulators. And finally, the architecture level consists of the trace-driven architecture simulation models. Preliminary simulation results show that, despite the high abstraction level at which is simulated, good accuracy can be obtained. operations. This translation is guided by a description of variables used in the kernel function. Such a description provides information on the type and location of variables, i.e. register based.