Monte-Carlo algorithms for layout density control

Japanese Journal of Applied Physics, 2007

The whole process of stochastic lithography simulation combined with an electron-beam module, could be useful in the validation of design rules taking into account fine details such as line-edge roughness, and for simulating the layout before actual fabrication for design inconsistencies. Material and process parameters can no more be considered of second order importance in high-density designs. Line-width roughness quantification should accompany CD measurements since it could be a large fraction of the total CD budget. An example of the effects of exposure, material and processes on layouts are presented in this work using a combination of electron beam simulation for the exposure part, stochastic simulations for the modeling of resist film, the post-exposure bake, resist dissolution, and a simple analytic model for resist etching. Particular examples of line-width roughness and critical dimension non-uniformity due to, material, and process effects on the gate of a standard CMOS inverter layout are presented.

2007 IEEE/SEMI Advanced Semiconductor Manufacturing Conference (ASMC), 2007

2009

Given a list with simple polygons and a sampling grid geometry, we calculate the sample (greyscale) value of each grid pixel, such that the residual error in a certain norm is suciently small, taking into account that the amount of computational operations should be minimal.

Integration, 2017

In this paper, a methodology for automatic generation of placement templates for analog integrated circuit design targeted to state-of-the-art optimization-based layout-aware circuit-sizing flows, is proposed. The multiobjective optimization-based placement template generator inputs a Pareto set of sizing solutions and outputs a set of optimal sizing-independent non-slicing B*-tree floorplan representations, i.e., placement templates. Those templates fit the current state of the optimization process and are used within the layout-aware synthesis methodology to generate the floorplan of the following candidate solutions. This innovative methodology combines the advantages of template-based placement approaches, due to its fast packing, with the optimization-based ones, presenting floorplan solutions with improved compactability through the complete evolution of the Pareto set, completely eliminating the template setup effort. Moreover, as the placement template generator runs in parallel with the layout-aware loop, it has no impact on the overall execution time. Experimental results show that the proposed methodology outperforms state-of-the-art multi-template layoutaware synthesis approaches by achieving smaller placement areas for the same performances earlier in the optimization, and further, with a strongly reduced setup effort.

Metrology, Inspection, and Process Control for Microlithography XXI, 2007

The whole process of stochastic lithography simulation combined with an electron-beam module, could be useful in the validation of design rules taking into account fine details such as line-edge roughness, and for simulating the layout before actual fabrication for design inconsistencies. Material and process parameters can no more be considered of second order importance in high-density designs. Line-width roughness quantification should accompany CD measurements since it could be a large fraction of the total CD budget. An example of the effects of exposure, material and processes on layouts are presented in this work using a combination of electron beam simulation for the exposure part, stochastic simulations for the modeling of resist film, the post-exposure bake, resist dissolution, and a simple analytic model for resist etching. Particular examples of line-width roughness and critical dimension non-uniformity due to, material, and process effects on the gate of a standard CMOS inverter layout are presented.

SCS 2003. International Symposium on Signals, Circuits and Systems. Proceedings (Cat. No.03EX720), 2000

The manufacturing complexity at the 90nm and 65nm technology nodes severally impacts the design. The traditional use of design rule based verification is no longer a guarantee of high yield once the chip has been manufactured. This paper describes many of the trends behind this phenomenon.

Proceedings of the ASP-DAC '99 Asia and South Pacific Design Automation Conference 1999 (Cat. No.99EX198), 1999

In the past two decades, the simulated annealing technique has been considered as a powerful approach to handle many NP-hard optimization problems in VLSI designs. Recently, a new Monte Carlo and optimization technique, named simulated tempering, was invented and has been successfully applied to many scientific problems, from random field Ising modeling to the traveling salesman problem. It is designed to overcome the drawback in simulated annealing when the problem has a rough energy landscape with many local minima separated by high energy barriers. In this paper, we have successfully applied a version of relaxed simulated tempering to slicing floorplan design with consideration of both area and wirelength optimization. Good experimental results were obtained.

2002

This paper addresses a Very Large Scale Integrated (VLSI) design problem that belongs to the NP-hard class. The Gate Matrix Layout problem has strong applications on the chip-manufacturing industry. A Memetic Algorithm is employed to solve a set of benchmark instances, present in previous works in the literature. Beyond the results found for these instances, another goal of this paper is to study how the use of multiple populations and different migration strategies affects the algorithm's performance. This comparison has shown to be fruitful, sometimes producing a strong performance improvement over single population approaches.

Nonconvex Optimization and Its Applications

The enormous size and complexity of current and future integrated circuits (IC's) presents a host of challenging global, combinatorial optimization problems. As IC's enter the nanometer scale, there is increased demand for scalable and adaptable algorithms for VLSI physical design: the transformation of a logicaltemporal circuit specification into a spatially explicit one. There are several key problems in physical design. We review recent advances in multiscale algorithms for three of them: partitioning, placement, and routing.

2020

IEEE Transactions on Very Large Scale Integration Systems, 2001

Floorplanning is a crucial phase in VLSI physical design. The subsequent placement and routing of the cells/modules are coupled very closely with the quality of the floorplan. A widely used technique for floorplanning is simulated annealing. It gives very good floorplanning results but has major limitation in terms of run time. For circuit sizes exceeding tens of modules simulated annealing is not practical. Floorplanning forms the core of many synthesis applications. Designers need faster prediction of system metrics to quickly evaluate the effects of design changes. Early prediction of metrics is imperative for estimating timing and routability. In this work we propose a constructive technique for predicting floorplan metrics. We show how to modify the existing top-down partitioning-based floorplanning to obtain a fast and accurate floorplan prediction. The prediction gets better as the number of modules and flexibility in the shapes increase. We also explore applicability of the traditional sizing theorem when combining two modules based on their sizes and interconnecting wirelength. Experimental results show that our prediction algorithm can predict the area/length cost function normally within 5-10% of the results obtained by simulated annealing and is, on average, 1000 times faster.

IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2010

The gap between VLSI technology and fabrication technology leads to strong refractive effects in lithography. Consequently, it is a huge challenge to reliably print layout features on wafers. The quality and robustness of lithography directly depend on layout patterns. It becomes imperative to consider the manufacturability issue during layout design such that the burden of lithography process can be alleviated. In this paper, three algorithms, namely, cell flipping algorithm, single row optimization approach and multiple row optimization approach, are proposed to tune any existing cell placement to be lithography friendly. These algorithms are based on dynamic programming and graph theoretic approaches, and can provide different tradeoff between critical dimension (CD) variation reduction and wirelength increase. Using lithography simulations, our experimental results demonstrate that over 15% CD variation reduction can be obtained in post-OPC stage by the new approaches while only less than 1% additional wire is introduced.

Design Automation Conference, 2003. Proceedings of the ASP-DAC 2003. Asia and South Pacific, 2003

In traditional floorplanners, area minimization is an important issue. Due to the recent advances in VLSI technology, the number of transistors in a design and their switching speeds are increasing rapidly. This results in the increasing importance of interconnect delay and routability of a circuit. We should consider interconnect planning and buffer planning as soon as possible. In this paper, we propose a method to reduce interconnect cost of a floorplan by searching alternative packings. We found that if a floorplan F contains some rectangular supermodules, we can rearrange the blocks in the supermodule to obtain a new floorplan with the same area as F but possibly with a smaller interconnect cost. Experimental results show that we can always reduce the interconnect cost of a floorplan without any penalty in area and runtime by using this method.

2008

2003

Chemical-mechanical planarization (CMP) and other manufacturing steps in very deep-submicron VLSI have varying effects on device and interconnect features, depending on the local layout density. To improve manufacturability and performance predictability, area fill features are inserted into the layout to improve uniformity with respect to density criteria. However, the performance impact of area fill insertion is not considered by any fill method in the literature. In this paper, we first review and develop estimates for capacitance and timing overhead of area fill insertions. We then give the first formulations of the Performance Impact Limited Fill (PIL-Fill) problem with the objective of either minimizing total delay impact (MDFC) or maximizing the minimum slack of all nets (MSFC), subject to inserting a given prescribed amount of fill. For the MDFC PIL-Fill problem, we describe three practical solution approaches based on Integer Linear Programming (ILP-I and ILP-II) and the Greedy method. For the MSFC PIL-Fill problem, we describe an iterated greedy method that integrates call to an industry static timing analysis tool. We test our methods on layout testcases obtained from industry. Compared with the normal fill method [3], our ILP-II method for MDFC PIL-Fill problem achieves between 25% and 90% reduction in terms of total weighted edge delay (roughly, a measure of sum of node slacks) impact while maintaining identical quality of the layout density control; and our iterated greedy method for MSFC PIL-Fill problem also shows significant advantage with respect to the minimum slack of nets on post-fill layout.