Area fill synthesis for uniform layout density

IEEE Transactions on Computer-aided Design of Integrated Circuits and Systems, 1999

In very deep-submicron very large scale integration (VLSI), manufacturing steps involving chemical-mechanical polishing (CMP) have varying effects on device and interconnect features, depending on local characteristics of the layout. To reduce manufacturing variation due to CMP and to improve performance predictability and yield, the layout must be made uniform with respect to certain density criteria, by inserting "fill" geometries into the layout. To date, only foundries and special mask data processing tools perform layout post-processing for density control. In the future, better convergence of performance verification flows will depend on such layout manipulations being embedded within the layout synthesis (place-and-route) flow. In this paper, we give the first realistic formulation of the filling problem that arises in layout optimization for manufacturability. Our formulation seeks to add features to a given process layer, such that 1) feature area densities satisfy prescribed upper and lower bounds in all windows of given size and 2) the maximum variation of such densities over all possible window positions in the layout is minimized. We present efficient algorithms for density analysis, notably a multilevel approach that affords usertunable accuracy. We also develop exact solutions to the problem of fill synthesis, based on a linear programming approach. These include a linear programming (LP) formulation for the fixeddissection regime (where density bounds are imposed on a predetermined set of windows in the layout) and an LP formulation that is automatically generated by our multilevel density analysis. We briefly review criteria for fill pattern synthesis, and the paper then concludes with computational results and directions for future research.

2003

Chemical-mechanical planarization (CMP) and other manufacturing steps in very deep-submicron VLSI have varying effects on device and interconnect features, depending on the local layout density. To improve manufacturability and performance predictability, area fill features are inserted into the layout to improve uniformity with respect to density criteria. However, the performance impact of area fill insertion is not considered by any fill method in the literature. In this paper, we first review and develop estimates for capacitance and timing overhead of area fill insertions. We then give the first formulations of the Performance Impact Limited Fill (PIL-Fill) problem with the objective of either minimizing total delay impact (MDFC) or maximizing the minimum slack of all nets (MSFC), subject to inserting a given prescribed amount of fill. For the MDFC PIL-Fill problem, we describe three practical solution approaches based on Integer Linear Programming (ILP-I and ILP-II) and the Greedy method. For the MSFC PIL-Fill problem, we describe an iterated greedy method that integrates call to an industry static timing analysis tool. We test our methods on layout testcases obtained from industry. Compared with the normal fill method [3], our ILP-II method for MDFC PIL-Fill problem achieves between 25% and 90% reduction in terms of total weighted edge delay (roughly, a measure of sum of node slacks) impact while maintaining identical quality of the layout density control; and our iterated greedy method for MSFC PIL-Fill problem also shows significant advantage with respect to the minimum slack of nets on post-fill layout.

Proceedings Twelfth International Conference on VLSI Design. (Cat. No.PR00013), 1999

To reduce manufacturing variation due to chemicalmechanical polishing and to improve yield, layout must be made uniform with respect to density criteria. This is achieved by layout postprocessing to add ll geometries, either at the foundry or, for better convergence of performance veri cation ows, during layout synthesis 10]. This paper proposes a new min-variation objective for the synthesis of ll geometries. Within the so-called xed-dissection regime (where density bounds are imposed on a predetermined set of windows in the layout), we exactly solve the min-variation objective using a linear programming formulation. We also state criteria for ll pattern synthesis, and discuss additional criteria that apply when ll must be grounded for predictability of circuit performance. We believe that density control for CMP will become an important research topic in the VLSI design-manufacturing interface over the next several years.

Materials Chemistry and Physics, 1995

In the next decade, it is expected that integrated circuits having 5 to 7 levels of metal will be common in VLSI technologies with linear interconnect densities approaching 200 meters/cm2/level. Multilevel interconnect technology needs are presently generating processing and structural issues which will dominate the future manufacturing yield and performance of these integrated circuits. The challenge of meeting these needs will require a concurrent improvement in design and manufacturing simplicity and cleanliness. This presentation will examine the architectural needs of future multilevel metal systems in light of the lithography, materials, and electrical requirements which must be addressed by the interconnect engineer. A comparison of interconnect systems based on different conductor materials will be presented.

Proceedings of ASP-DAC '97: Asia and South Pacific Design Automation Conference, 1997

This paper presents an overview of recent advances on modeling and layout optimization of devices and interconnects for high-performance VLSI circuit design under the deep submicron technology. First, we review a number of interconnect and driver/gate delay models, which are most useful to guide the layout optimization. Then, we summarize the available performance optimization techniques for VLSI device and interconnect layout, including driver and transistor sizing, transistor ordering, interconnect topology optimization, optimal wire sizing, optimal buffer placement, and simultaneous topology construction, buffer insertion, buffer and wire sizing. The efficiency and impact of these techniques will be discussed in the tutorial.

Proceedings of the ASP-DAC '99 Asia and South Pacific Design Automation Conference 1999 (Cat. No.99EX198), 1999

Certain manufacturing steps in very deep submicron VLSI involve chemical-mechanical polishing CMP which has varying e ects on device and interconnect features, depending on local layout characteristics. To reduce manufacturing variation due to CMP and to improve yield and performance p r edictability, the layout needs to be m a d e u n iform with respect to certain density criteria, by inserting ll" geometries into the layout. This paper presents an efcient multilevel approach to density analysis that a ords user-tunable accuracy. We also develop exact ll synthesis solutions based o n c ombining multilevel analysis with a linear programming approach. Our methods apply to both at and hierarchical designs.

1999

Abstract We propose a new VLSI layout methodology which addresses the main problems faced in Deep Sub-Micron (DSM) integrated circuit design. Our layout “fabric” scheme eliminates the conventional notion of power and ground routing on the integrated circuit die. Instead, power and ground are essentially “pre-routed” all over the die. By a clever arrangement of power/ground and signal pins, we almost completely eliminate the capacitive effects between signal wires.

IEEE Transactions on Semiconductor Manufacturing, 1997

In this paper, we address the problem of identifying and evaluating "critical features" in an integrated circuit (IC) layout. The "critical features" (e.g., nested elbows and open ends) are areas in the layout that are more prone to defects during photolithography. As feature sizes become smaller (sub-micron range) and as the chip area becomes larger, new process techniques (such as, using phase shifted masks for photolithography), are being used. Under these conditions, the only means to design compact circuits with good yield capabilities is to bring the design and process phases of IC manufacturing closer. This can be accomplished by integrating photolithography simulators with layout editors. However, evaluation of a large layout using a photolithography simulator is time consuming and often unnecessary. A much faster and efficient method would be to have a means of automatically identifying "critical features" in a layout and then evaluate the "critical features" using a photolithography simulator. Our technique has potential for use either to evaluate the limits of any new and nonconventional process technique in an early process definition phase or in a mask house, as a postprocessor to improve the printing capability of a given mask. This paper presents a CAD tool (An Integrated CAD Framework) which is built upon the layout editor, Magic, and the process simulator, Depict 3.0, that automatically identifies and evaluates "critical features."

2008

Case Studies on Lithography-Friendly VLSI Circuit Layout.

CMP fills are inserted to make metal density uniform and hence reduce post-polish height variations. Classical methods to insert fills focus on metal density uniformity, but do not take into consideration or are unable to minimize the impact of fills on circuit performance. In this paper, we develop a fill insertion method that heuristically minimizes coupling capacitance increase due to fill. Our optimization methodology builds on fill insertion guidelines previously developed in, e.g., and . Experiments show that the proposed optimization methods can reduce fill impact on coupling capacitances by up to 85% for 30% pattern density and up to 65% for 60% pattern density cases.