Building Timing Predictable Embedded Systems

Proc. 1st International Workshop on …, 2009

In general-purpose software applications, computation time is just a quality factor: faster is better. In cyber-physical systems (CPS), however, computation time is a correctness factor: missed deadlines for hard real-time applications, such as avionics and automobiles, can result in devastating, life-threatening consequences. Although many modern modeling languages for CPS include the notion of time, implementation languages such as C lack any temporal semantics. Consequently, models and programs for CPS are neither portable nor guaranteed to execute correctly on the real system; timing is merely a side effect of the realization of a software system on a specific hardware platform. In this position paper, we present the research initiative for a precision timed (PRET) infrastructure, consisting of languages, compilers, and microarchitectures, where timing is a correctness factor. In particular, the timing semantics in models and programs must be preserved during compilation to ensure that the behavior of real systems complies with models. We also outline new research and design challenges present in such an infrastructure.

ACM Transactions on Design Automation of Electronic Systems, 1998

We address the problem of timing constraint derivation and validation for reactive and real-time embedded systems. We assume that such a system is structured into its tasks, and the structure is modeled using a task graph. Our solution uses the timing behavior committed by the environment to the system rst to derive the timing constraints on the system's internal behavior and then use them to derive and validate the timing constraints on the system's external behavior. Our solution consists of the following contributions: a generalized task graph model, a comprehensive classi cation of timing constraints, algorithms for derivation and validation of timing constraints of the system modeled in the generalized task graph model, a codesign methodology that combines the model and the algorithms, and the implementation of this methodology in a tool called RADHA-RATAN. The main advantages of our solution are that it simpli es the problem of ensuring timing correctness of the system by reducing the complexity of the problem from system level to task level, and that it makes the codesign methodology timing-driven in that our solution makes it possible to maintain a handle on the system's timing correctness from very early stages in the system's design ow.

The demand for predictable timing behavior is characteristic for real-time applications. Experience has shown that this property cannot be achieved by software alone but rather requires support from the processor. This situation is analyzed and mapped to a design rationale for SPEAR (Scalable Processor for Embedded Applications in Real-time Environments), a processor that has been designed to meet the specific temporal demands of real-time systems. At the hardware level, SPEAR guarantees interrupt response with minimum temporal jitter and minimum delay. Furthermore, the processor provides an instruction set that only has constant-time instructions. At the software level, SPEAR supports the implementation of temporally predictable code according to the single-path programming paradigm. Altogether, these features support writing of code with minimal jitter and provide the basis for exact temporal predictability. Experimental results show that SPEAR indeed exhibits the anticipated high...

2008

This paper discusses why the extensive scientific results on predicting embedded systems temporal behavior never, or very seldom, reaches the industrial community. We also point out the main issues that the scientific community should focus on in order to facilitate industrial-strength timing predictions. The core problem is that the scientific community uses too simplistic or research oriented timing models. The models stemming from academy do not fit well with the structure of real systems. Thus, extracting a timing model that is amenable for analysis may prove prohibitively difficult. And even if a model can be extracted, it may not capture real system scenarios well. Thus, results from analyzing these models do not reflect real system behavior, leading to unnecessary pessimistic timing predictions. In recent years, response-time analysis has matured to a degree where models can express complex system behaviors and analysis results are relatively tight with respect to real system behavior. However, in order to fully reach its potential, and be accepted by industry, several improvements of the technique are needed. First, behaviors that are commonly used in industrial systems (such as message passing and client/server-patterns) must be adequately captured by the timing models. Second, unnecessary pessimism in the analysis must be removed (i.e. the analysis results must correlate well with actual system behavior by providing minimal overestimation). Third, correlated behaviors of different parts of the systems must be accounted for (i.e. not all tasks will experience the worst case execution times at the same time).

… -Alpes, http://hal. inria. fr/inria …, 2009

1994

Abstract Predictability-the ability to foretell that an implementation will not violate a set of specified reliability and timeliness requirements-is a crucial, highly desirable property of responsive embedded systems. This paper overviews a development methodology for responsive systems, which enhances predictability by eliminating potential hazards resulting from physically-unsound specifications.

Abstract—Building safety-critical real-time systems out of inexpensive, non-real-time, Commercial Off-the-Shelf (COTS) components is challenging. Although COTS components generally offer high performance, they can occasionally incur significant timing spikes. To prevent this, we propose controlling the operating point of shared resources, for example main memory, to maintain it below its saturation limit. This is necessary because the low-level arbiters of these shared resources are not typically designed to provide real-time ...

Next Generation Design and Verification Methodologies for Distributed Embedded Control Systems, 2007

In this paper we address the problems of schedule synthesis and timing verification for component based architectures in embedded systems. We consider a component to be a set of tasks with response times that lie within specified intervals. When a set of components is deployed to implement a desired functionality, we want to guarantee that the components can achieve the timing constraints of the application. We solve the associated synthesis and verification problems using the framework of timed interface automata and timed games.