An interconnect-centric design flow for nanometer technologies

2016

This thesis proposes a graph-based maze routing and buffer insertion algorithm for nanometer Very Large Scale Integration (VLSI) layout designs. The algorithm is called Hybrid Routing Tree and Buffer insertion with Look-Ahead (HRTB-LA). In recent VLSI designs, interconnect delay becomes a dominant factor compared to gate delay. The well-known technique to minimize the interconnect delay is by inserting buffers along the interconnect wires. In conventional buffer insertion algorithms, the buffers are inserted on the fixed routing paths. However, in a modern design, there are macro blocks that prohibit any buffer insertion in their respective area. Most of the conventional buffer insertion algorithms do not consider these obstacles. In the presence of buffer obstacles, post routing algorithm may produce poor solution. On the other hand, simultaneous routing and buffer insertion algorithm offers a better solution, but it was proven to be NP-complete. Besides timing performance, power d...

6th International Workshop on HLS Proc, 1992

Until recently, the emphasis in automated datapath construction was optimization through reduction of resources due to area constraints. Lately, this constraint has relaxed somewhat with the reduction of minimal feature sizes and the expansion of die sizes. This shift has ...

Electronics, 2017

As we increasingly use advanced technology nodes to design integrated circuits (ICs), physical designers and electronic design automation (EDA) providers are facing multiple challenges, firstly, to honor all physical constraints coming with cutting-edge technologies and, secondly, to achieve expected quality of results (QoR). An advanced technology should be able to bring better performances with minimum cost whatever the complexity. A high effort to develop out-of-the-box optimization techniques is more than needed. In this paper, we will introduce a new routing technique, with the objective to optimize timing, by only acting on routing topology, and without impacting the IC Area. In fact, the self-aligned double patterning (SADP) technology offers an important difference on layer resistance between SADP and No-SADP layers; this property will be taken as an advantage to drive the global router to use No-SADP less resistive layers for critical nets. To prove the benefit on real test cases, we will use Mentor Graphics' physical design EDA tool Nitro-SoC™ and several 7 nm technology node designs. The experiments show that worst negative slack (WNS) and total negative slack (TNS) improved up to 13% and 56%, respectively, compared to the baseline flow.

IAEME PUBLICATION, 2021

In the course of recent years, the semiconductor business has been driven by Moore's law, which has accurately anticipated that the quantities of semiconductors incorporated on a chip will twofold every 18 two years, bringing about outstanding development in chip intricacy. This pattern was initially conjecture in 1965 dependent on just five information focuses, the biggest of which compared to only 64 On to Chip semiconductors. Incredibly, it's anything but an exact indicator from that point until the present 3 billion semiconductor plans. To some degree, this is because of the semiconductor business' endeavors to make Moore's "law" an unavoidable outcome, through essential plans, for example, those illustrated in the International Technology Roadmap for Semiconductors, to drive the business and the general store network to accomplish and support this noteworthy development. On the interest side, this development has been prodded on by the colossal craving for more up to date, quicker, less expensive, and more versatile chips that have altered our lifestyle, making an inescapable engraving across regions like logical figuring, remote correspondence, the web, electronic diversion, advanced photography and videography, medical services, security, and banking. There are four critical obstructions to the continuation of this pattern. In the first place, Moore's law has been worked with by persistently contracting semiconductor and wire measurements, so more gadgets can be created inside a similar silicon region. Nonetheless, these element sizes are presently down to several nanometers, where the expense of assembling is high. Second, despite the fact that Moore's law makes more gadgets accessible on a chip, running such a large number of them scatters unsuitably high force and creates inordinate warmth. These impediments imply that a more modest part, everything being equal, can stay on at a given time, and inventive force conveyance and warm administration techniques are fundamental. As one piece of the arrangement, single- centre processors have cleared a path for multicore processors, which empower better force and warm administration. Third, as more gadgets have been put on a chip, there is a requirement for more noteworthy correspondence between the gadgets. Traditional ideal models that utilization committed wires or transports don't scale well with framework sizes, and clever thoughts like framework On to Chip, networks-On to Chip (NoCs) and so forth are acquiring footing for future On to Chip correspondence designs, especially multicores. What's more, in conclusion, interconnect crosstalk commotion has genuine ramifications as it influences the sign honesty of the framework. An exact examination of crosstalk impacts is fundamental and a basic issue. This issue is effectively models and examinations the crosstalk impacts in current-mode flagging (CMS) multilinecoupled-disseminated obstruction inductance-capacitance (RLC) interconnect. This spurred by these difficulties and identifies with advancing interconnects for multicore chips, which is generally acknowledged as the significant execution bottleneck in future plans. This desk work is to plan and advancement of interconnect; to displayed RCL interconnect line utilizing trademark impedance of line, and to contemplate power conveyance in multicore chips.

IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2000

This paper studies buffer block planning for interconnect planning and prediction in deep submicron designs. We first introduce the concept of feasible region for buffer insertion, and derive its closedform formula. We observe that the feasible region for a buffer is quite large in general even under fairly tight delay constraint. Therefore, FR gives us a lot of flexibility to plan for buffer locations. We then develop an effective buffer block planning algorithm to perform buffer clustering such that design objectives such as overall chip area and the number of buffer blocks can be minimized. Effective buffer block planning can plan and predict system-level interconnect by construction, so that accurate interconnect information can be used in early design stages to ensure design closure.

In current deep sub-micron chip design, interconnect effects start to dominate the chip's performance. Therefore, the design flow has to become more interconnect-oriented. To limit the number of design iterations (and hence improve the time-to-market) one has to estimate interconnect param- eters and their impact as early as possible. This is the goal of the field of System-Level Interconnect Prediction. New research results are becoming available and the last couple of years have brought both more interest and more progress in the field than in the thirty years before. This paper is an introduction to the field and provides an overview of some of the recent advances in system-level interconnect prediction, including several applica- tions.

VLSI: Systems on a Chip, 2000

Architectural synthesis tools map algorithms to architectures under various constraints and quickly providc estimations of area and performance. However. these tools do not take the intcrconnection cost into account whereas it bccomes predominant with the technology dccrease and the application complexity incrcasc. A way to control costly interconnections during the architcctural proccss is prcscnted in this paper. Architcctural synthesis, digital ASIC dcsign, sub-micron tcchnologies, interconncction cost The original version of this chapter was revised: The copyright line was incorrect. This has been corrected. The Erratum to this chapter is available at DOI:

1999

In this paper we develop a set of interconnect delay estimation models with consideration of various layout optimizations, including optimal wire-sizing OWS, simultaneous driver and wire sizing SDWS, and simultaneous bu er insertion sizing and wire sizing BISWS. These models have been tested on a wide range of parameters and shown to have about 90 accuracy on average compared with those from running complex optimization algorithms directly followed by HSPICE simulations. Moreover, our models run in constant time in practice. As a result, these simple, fast, yet accurate models are expected t o b e very useful for a wide variety of purposes, including layout-driven logic and high level synthesis, performance-driven oorplanning, and interconnect planning.

2008

Abstract This article presents a software framework for communication infrastructure synthesis of distributed systems, which is critical for overall system performance in communication-based design. Particular emphasis is given to on-chip interconnect synthesis of multicore designs.

2004

For multi-gigahertz synchronous designs in nanometer technologies, multiple clock cycles are needed to cross the global interconnects, thus making it necessary to have pipelined global interconnects. In this paper we present an architecture-level synthesis solution to support automatic pipelining of on-chip interconnects. Specifically, we extend the recently proposed Regular Distributed Register (RDR) micro-architecture to support interconnect pipelining. We formulate a novel global interconnect sharing problem for global wiring minimization and show that it is polynomial time solvable by transformation to a special case of the real-time scheduling problem. Experimental results show that our approach matches or exceeds the RDR-based approach in performance, with a significant wiring reduction of 15% to 21%.

IEEE International Conference on Computer Design: VLSI in Computers and Processors, 2004. ICCD 2004. Proceedings., 2004

In Deep Sub-Micron (DSM) technologies, interconnects play a crucial role in the correct functionality and largely impact the performance of complex System-on-Chip (SoC) designs. For technologies of 0.25µm and below, wiring capacitance dominates gate capacitance, thus rapidly increasing the interconnect-induced delay. Moreover, the coupling capacitance becomes a significant portion of the on-chip total wiring capacitance, and coupling between adjacent wires cannot be considered as a second-order effect any longer. As a consequence, the traditional top-down design methodology is ineffective, since the actual wiring delays can be computed only after layout parasitic extraction, when the physical design is completed. Fixing all the timing violations often requires several time-consuming iterations of logical and physical design, and it is essentially a trial-and-error approach. Increasingly tighter time-to-market requirements dictate that interconnect parasitics must be taken into account during all phases of the design flow, at different level of abstractions. However, given the aggressive technology scaling trends and the growing design complexity, this approach will only temporarily ameliorate the interconnect problem. We believe that in order to achieve gigascale designs in the nanometer regime, a novel design paradigm, based on new forms of regularity and newly created IP (Intellectual Property) blocks must be developed, to provide a direct path from system-level architectural exploration to physical implementation.

… of Computing Systems- …, 2007

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2002

In this paper, we study wire width planning for interconnect performance optimization in an interconnect-centric design flow. We first propose some simplified, yet near-optimal wire sizing schemes, using only one or two discrete wire widths. Our sensitivity study on wire sizing optimization further suggests that there exists a small set of "globally" optimal wire widths for a range of interconnects. We develop general and efficient methods for computing such a "globally" optimal wire width design and show rather surprisingly that using only two "predesigned" widths for each metal layer, we are still able to achieve close to optimal performance compared with that by using many possible widths, not only for one fixed length, but also for all wire lengths assigned at each metal layer. Our wire width planning can consider different design objectives and wire length distributions. Moreover, our method has a predictable small amount of errors compared with optimal solutions. We expect that our simplified wire sizing schemes and wire width planning methodology will be very useful for better design convergence and simpler routing architectures.

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1998

The significant role played by interconnects in determining the speed and chip size of very-large-scale integrated circuits (VLSI's) necessitates the development of new processes and tools for almost every device generation. Since such development usually requires lead times of several years, it has become essential to know, several years in advance, the various interconnect parameters for a particular generation. In this paper, a tool for optimizing interconnect parameters is presented. The formulation of an optimization problem that can be solved using standard algorithms is shown to be possible, and the optimization results obtained for future device generations are discussed. These results can be used to construct an interconnect technology roadmap. Last, shortcomings of and possible improvements to existing system-level critical path models are discussed.

Proceedings of the 36th ACM/IEEE conference on Design automation conference - DAC '99, 1999

This paper reports two sets of important results in our exploration of an interconnect-centric design flow for deep submicron (DSM) designs: (i) We obtain eficient yet accumte wiring area estimation models for optimal wire sizing (OWS). We also pwpose a simple metric to guide area-eficient performance optimization; (ii) Guided by our interconnect estimation models, we study the interconnect architecture planning problem for wirewidth designs. We achieve a rather surprising result which suggests that two pre-determined wire widths per metal layer are suficient to achieve near-optimal performance. This result will greatly simplify the muting architecture and tools for DSM designs. We believe that our interconnect estimation and planning results will have a significant impact on DSM designs.