On Hybrid Abstraction-level Models in Architecture Simulation

ACM Transactions on Architecture and Code Optimization, 2012

Simulation is a key tool for computer architecture research. In particular, cycle-accurate simulators are extremely important for microarchitecture exploration and detailed design decisions, but they are slow and, so, not suitable for simulating large-scale architectures, nor are they meant for this. Moreover, microarchitecture design decisions are irrelevant, or even misleading, for early processor design stages and high-level explorations. This allows one to raise the abstraction level of the simulated architecture, and also the application abstraction level, as it does not necessarily have to be represented as an instruction stream. In this paper we introduce a definition of different application abstraction levels, and how these are employed in TaskSim, a multi-core architecture simulator, to provide several architecture modeling abstractions, and simulate large-scale architectures with hundreds of cores. We compare the simulation speed of these abstraction levels to the ones in...

IEEE Computer Society Annual Symposium on VLSI, 2004

Abstraction is a powerful technique for the design and implementation of complex systems. A model developed at a higher level of abstraction allows one to tackle complexity by initially hiding the details and elaborating them later. A higher level of abstraction typically has a positive effect on the simulation speed and ease of development of the model, but could affect the accuracy of the model developed. In this paper, we study the effect of model abstraction of a peripheral device developed at a higher level of abstraction using SystemC, and at the register transfer level using Verilog. The parameters compared are accuracy, simulation speed, flexibility, time to develop, code length and ease of verification. In our study we show that by raising the level of abstraction, one not only achieves better simulation speed, flexibility, ease of verification but also reduces time to develop and shorten code length. All this is achieved while being able to maintain almost the same accuracy.

E3S Web of Conferences, 2021

Simulating systems on a chip (SoC) even before starting its productivity makes it possible to validate the correct functioning of the systems, also avoiding the manufacture of defective chips. However, low-level design and system complexity makes verification and simulation more complicated and time consuming. The classification of the different levels of abstraction from lowest to highest generally depends on the estimation accuracy of the system performance and the speed of simulation. The RTL (Register Transfer Level) abstraction level allows efficient description at gate level with good precision. Therefore, RTL program are slowly simulated. Simulation speed usually depends on the size of the platform used, which is not the case for transaction level modeling (TLM) to achieve simulation speed based on the exchange of transactions between system modules. This work aims to give a detailed description of the different levels of abstraction with the main advantages, and disadvantage...

Proceedings of the 2006 …, 2006

The Sesame modeling and simulation framework aims at efficient system-level design space exploration of embedded multimedia systems. A primary objective of Sesame is the exploration at multiple levels of abstraction. As such, it targets gradual refinement of its (initially abstract) architecture performance models while maintaining architectureindependent application specifications. In this paper, we present a mixed-level co-simulation method, called trace calibration, for incorporating external simulators into Sesame's abstract system-level performance models. We show that trace calibration only requires minor modification of the incorporated simulators and that performance overheads due to co-simulation are minimal. Also, we show that trace calibration transparantly supports distributed co-simulation, allowing for effectively reducing the system-level simulation slowdown due to the incorporation of lower-level simulators.

2007 Asia and South Pacific Design Automation Conference, 2007

Embedded software is playing an increasing role in todays SoC designs. It allows a flexible adaptation to evolving standards and to customer specific demands. As software emerges more and more as a design bottleneck, early, fast, and accurate simulation of software becomes crucial. Therefore, an efficient modeling of programmable processors at high levels of abstraction is required. In this article, we focus on abstraction of computation and describe our abstract modeling of embedded processors. We combine the computation modeling with task scheduling support and accurate interrupt handling into a versatile, multi-faceted processor model with varying levels of features. Incorporating the abstract processor model into a communication model, we achieve fast co-simulation of a complete custom target architecture for a system level design exploration. We demonstrate the effectiveness of our approach using an industrial strength telecommunication example executing on a Motorola DSP architecture. Our results indicate the tremendous value of abstract processor modeling. Different feature levels achieve a simulation speedup of up to 6600 times with an error of less than 8% over a ISS based simulation. On the other hand, our full featured model exhibits a 3% error in simulated timing with a 1800 times speedup.

Proceedings of the 2005 conference on Asia South Pacific design automation - ASP-DAC '05, 2005

Current and future SoC will contain an increasing number of heterogeneous multiprocessor subsystems combined with a complex communication architecture to meet flexibility, performance and cost constraints. The early validation of such complex MP-SoC architectures is a key enabler to manage this complexity and thus to enhance design productivity. In this paper, we describe an abstract, high level CPU subsystem model that captures the specificities of such MP-SoC architectures, along with a timed co-simulation environment to perform early exploration of the entire HW/SW design. The model is based on the Hardware Abstraction Layer (HAL) concept allowing the validation of complex applications written on top of real-life operating systems. Experimentation with a MPEG4 application proves the interest of the proposed methodology.

2000

Know-how is the most useful mean for designing new processors before a complete hardware description. The integration rate is increasing very quickly and the timeto-market has to be dramatically reduced because of the rapid evolution of technology. Therefore, reuse and rapid-prototyping are definitely a major issue to integrate existing architectures and to design new ones. SEP is an object-oriented framework which attends these problems. This paper intends to show major problems and solutions in simulation due to our simplification choices and in particular due to a not typed specification. It also presents the service feature which is a major enhancement to SEP and allow some validation of static properties about the rapidprototyped model and its associated instruction-set. In this paper some examples related to the modelling of an industrial bi-core architecture from VLSI Technologya subsidiary of Philips Semiconductors-are used to illustrate our method.

EURASIP Journal on Embedded Systems

The high complexity of modern embedded systems impels designers of such systems to model and simulate system components and their interactions in the early design stages. It is therefore essential to develop good tools for exploring a wide range of design choices at these early stages, where the design space is very large. This paper provides an overview of our system-level modeling and simulation environment, Sesame, which aims at efficient design space exploration of embedded multimedia system architectures. Taking Sesame as a basis, we discuss many important key concepts in early systems evaluation, such as Y-chart-based systems modeling, design space pruning and exploration, trace-driven cosimulation, and model calibration.

EURASIP Journal on …, 2007

The high complexity of modern embedded systems impels designers of such systems to model and simulate system components and their interactions in the early design stages. It is therefore essential to develop good tools for exploring a wide range of design choices at these early stages, where the design space is very large. This paper provides an overview of our system-level modeling and simulation environment, Sesame, which aims at efficient design space exploration of embedded multimedia system architectures. Taking Sesame as a basis, we discuss many important key concepts in early systems evaluation, such as Y-chart-based systems modeling, design space pruning and exploration, trace-driven cosimulation, and model calibration.

Design & Test of Computers, …, 2011

MODERN EMBEDDED-SYSTEM platforms often integrate various types of processing elements into the system, including general-purpose CPUs, applicationspecific instruction-set processors (ASIPs), digitalsignal processors (DSPs), and dedicated hardware accelerators. The large size and great complexity of these systems pose enormous challenges to traditional design and validation. System designers are forced to move to higher abstraction levels to cope with the many problems, which include many heterogeneous components, complex interconnects, sophisticated functionality, and slow simulation. At the electronic system level (ESL), system design and verification aim at a systematic top-down design methodology that successively transforms a given high-level specification model into a detailed implementation. As one example, the system-on-chip environment (SCE) is a refinement-based framework for heterogeneous multiprocessor SoC (MPSoC) design. The SCE, beginning with a system specification model described in the SpecC language, 2 implements a top-down ESL design flow based on the specifyexplore-refine methodology. The SCE automatically generates a set of transaction-level models (TLMs) with an increasing amount of implementation details through stepwise refinement, resulting in a pin-and cycle-accurate system implementation.