Adaptive Compilation for Reconfigurable Computers

2010

Abstract Reconfigurable computing platforms offer the promise of substantially accelerating computations through the concurrent nature of hardware structures and the ability of these architectures for hardware customization.

The Squeak Smalltalk virtual machine is used in several projects (Squeak, Pharo, Cuis, Context, NewSpeak) and has software implementations including the original interpreter, SqueakR (PyPy), SqueakJS (Javasscript) and Cog (JIT compiler) plus Sista (bytecode optimizer). SiliconSqueak is a microcoded-like processor with four caches which can be implemented in an FPGA or an ASIC to efficiently support both interpreters and adaptive compilation.

Compilation Techniques for Reconfigurable Architectures, 2008

This chapter describes the most prominent academic efforts on compilation and synthesis of application codes written in high-level programming languages to reconfigurable architectures. The maturity of some of the compilation and mapping techniques described in Chaps. 4 and 5, and the stability of the underlying reconfigurable technologies, have enabled the emergence of commercial compilation solutions, such as the MAP compiler from SRC Computers [292] and the High-Level Compiler from Nallatech [223], both of which support the mapping of programs written in a subset of the C programming language to FPGAs. In this chapter, we distinguish between compilation efforts that target finegrained commercially available reconfigurable devices, such as well-known FP-GAs, and efforts that target architectures with proprietary reconfigurable devices, typically coarse-grained devices. Despite their granularity distinction, and thus the different mapping techniques used, these efforts exhibit many commonalities. We begin with a brief historical perspective on early compilation efforts, which naturally focused on fine-grained architectures. We then describe various representative compilation efforts, highlighting their use of the transformations and mapping techniques described in the previous two chapters. We conclude by summarizing and highlighting the differences between the described compilation efforts.

Proceedings of 1998 Asia and South Pacific Design Automation Conference

Parallel …, 1999

This paper presents the Cameron Project 1 , which aims to provide a high level, algorithmic language and optimizing compiler for the development of image processing applications on Reconfigurable Computing Systems (RCSs). SA-C, a single assignment variant of the C programming language, is designed to exploit both coarse-grain and fine-grain parallelism in image processing applications. Khoros, a software development environment commonly used for image processing, has been modified to support SA-C program development.

1998

Field-Programmable Logic …, 2002

In addition to high performance requirements, future generation mobile telecommunications brings new constraints to the semiconductor design world. In order to associate the flexibility to the highperformances and the low-energy consumption needed by this application domain we have developed a functional level dynamically reconfigurable architecture, DART. Even if this architecture supports the processing complexity of the UMTS while allowing the portability of the devices and their evolutions, another challenge is to develop efficient high-level design tools. In this paper, we discuss about a methodology allowing the definition of such development tool based on the joint used of compilation and behavioral synthesis schemes.

2005

ROCCC (Riverside Optimizing Configurable Computing Compiler) is an optimizing C to HDL compiler targeting FPGA and CSOC (Configurable System On a Chip) architectures. ROCCC system is built on the SUIF-MACHSUIF compiler infrastructure. Our system first identifies frequently executed kernel loops inside programs and then compiles them to VHDL after optimizing the kernels to make best use of FPGA resources. This paper presents an overview of the ROCCC project as well as optimizations performed inside the ROCCC compiler.

Computer Systems: …, 2004

To answer new challenges, systems on chip need to gain flexibility and fpgas need to gain structure. We propose a general framework for SoC architectures and software tools in which different kind of processing units are programmed at high level. We show a reconfigurable unit suitable for this framework and we draw the outline of a supercompiler able to address such an architecture.

Computer, 2000

Initial performance results with FPGAs were impressive. However, commercial FPGAs have inherent shortcomings, which heretofore made reconfigurable computing impractical for mainstream computing: • Logic granularity. FPGAs are designed for logic replacement. The functional units' granularity is optimized to replace random logic, not to perform multimedia computations. Reconfigurable computing will change the way computing systems are designed, built, and used. PipeRench, a new reconfigurable fabric, combines the flexibility of general-purpose processors with the efficiency of customized hardware to achieve extreme performance speedup.