General iterative heuristics for VLSI multiobjective partitioning
Aiman H. El-Maleh2003, Proceedings of the 2003 International Symposium on Circuits and Systems, 2003. ISCAS '03.
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Abstract
The problem of partitioning appears in several areas ranging from VLSI, parallel programming, to molecular biology. The interest in finding an optimal partition especially in VLSI has been a hot issue in recent years. In VLSI circuit partitioning, the problem of obtaining a minimum cut is of prime importance. With current trends, partitioning with multiple objectives which includes power, delay and area, in addition to minimum cut is in vogue. In this paper, we engineer two iterative heuristics for the optimization of VLSI netlist bi-Partitioning. These heuristics are based on Genetic Algorithms (GAs) and Tabu Search (TS) and incorporate fuzzy rules in order to handle the multiobjective cost function. Both heuristics are applied to ISCAS-85/89 benchmark circuits and experimental results are reported and compared.
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The problem of partitioning appears in several areas ranging from VLSI, parallel programming, to molecular biology. The interest in finding an optimal partitioning especially in VLSI, and has been a hot issue in recent years. In VLSI circuit partitioning, the problem of obtaining a minimum cut was of prime importance. Furthermore, with current trends partitioning has become a multi-objective problem, where power, delay and area in addition to minimum cut, need to be optimized. In this paper we employ two iterative heuristics for the optimization of VLSI Netlist Bi-Partitioning. These heuristics are based on Genetic Algorithms (GAs) and Tabu Search (TS) [sadiq et al., 1999] respectively. Fuzzy rules are incorporated in order to design a multiobjective cost function. Both the techniques are applied to ISCAS-85/89 benchmark circuits and experimental results are reported and compared.
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The problem of partitioning appears in several areas ranging from VLSI, parallel programming, to molecular biology. The interest in finding an optimal partition especially in VLSI has been a hot issue in recent years. In VLSI circuit partitioning, the problem of obtaining a minimum cut is of prime importance. With current trends, partitioning with multiple objectives which includes power, delay and area, in addition to minimum cut is in vogue. In this paper, we engineer three iterative heuristics for the optimization of VLSI netlist bi-Partitioning. These heuristics are based on Genetic Algorithms (GAs), Tabu Search (TS) and Simulated Evolution (SimE). Fuzzy rules are incorporated in order to handle the multiobjective cost function. For SimE, fuzzy goodness functions are designed for delay and power, and proved efficient. A series of experiments are performed to evaluate the efficiency of the algorithms. ISCAS-85/89 benchmark circuits are used and experimental results are reported and analyzed to compare the performance of GA, TS and SimE. Further, we compared the results of the iterative heuristics with a modified FM algorithm, named PowerFM, which targets power optimization. PowerFM performs better in terms of power dissipation for smaller circuits. For larger sized circuits, SimE outperforms PowerFM in terms of all the three objectives, delay, number of nets cut, and power dissipation.
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The problem of partitioning appears in several areas ranging from VLSI, parallel programming, to molecular biology. The interest in finding an optimal partition especially in VLSI has been a hot issue in recent years. In VLSI circuit partitioning, the problem of obtaining a minimum cut is of prime importance. With current trends, partitioning with multiple objectives which includes power, delay and area, in addition to minimum cut is in vogue. In this paper, we engineer three iterative heuristics for the optimization of VLSI netlist bi-Partitioning. These heuristics are based on Genetic Algorithms (GAs), Tabu Search (TS) and Simulated Evolution (SimE). Fuzzy rules were incorporated in order to handle the multiobjective cost function. For SimE, fuzzy goodness functions are designed for delay and power, and proved efficient. A series of experiments are performed to evaluate the efficiency of the algorithms. ISCAS-85/89 benchmark circuits are used and experimental results are reported and analyzed to compare the performance of GA, TS and SimE.
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A VLSI chip can today contain millions of transistors and is expected to contain more than 100 million transistors in the next decade. This tremendous growth is made possible by the development of sophisticated design tools and software. To deal with the complexity of millions of components and to achieve a turn around time in terms of a couple of months, VLSI design tools must not only be computationally fast but also generate layouts close to optimal. The work in this thesis involves exploring algorithmic solutions to the problem of circuit layout in VLSI design. The exploration is an attempt to evaluate, design, improve and integrate the best combinatorial algorithms to solve the circuit layout problem. Advanced search heuristic techniques in the form of Tabu Search, GRASP and Genetic Algorithms are used extensively to solve most of the problems in circuit layout. We show in this thesis that new hybrid partitioning techniques based on the above mentioned heuristics outperform traditional heuristic methods. In fact, these novel approaches consistently find better solutions than other methods in a fraction of the time. A new placement algorithm that is suitable for standard cell layout is also presented. The initial placement is obtained using the partitioning algorithm. An efficient clustering based algorithm is developed to further reduce the complexity of circuit partitioning and placement and improve the performance of the design process in terms of quality and computation time. Finally, parallel implementations of the developed heuristics on a network of workstations are presented and significant speedups are reported. The ability of the hybrid heuristics to find near optimal solutions is assessed by comparing their performance with a general purpose mixed integer programming package. Experimental results indicate that our heuristics based on clustering and hybridization schemes give very good results and are suitable for VLSI circuits. v xv C.4 GRASP 2-Way partitioning .
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Key words: The relevance of VLSI in performance computing, telecommunications, and consumer electronics has been expanding progressively, and at a very hasty pace. In order to build complex digital logic circuits it is often essential to sub-divide multi -million transistors design into manageable pieces. Circuit partitioning is a general approach used to solve problems that are too large and complex to be handled at once. In partitioning, the problem is divided into small and manageable parts recursively, until the required complexity level is reached. In the area of VLSI, circuit complexity is rapidly multiplying, together with the reducing chip sizes; the integrated chips being produced today are highly sophisticated. There are many diverse problems that occur during the development phase of an IC that can be solved by using circuit partitioning which aims at obtaining the sub circuits with minimum interconnections between them. This paper aims at circuit partitioning using clust...
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