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2011, 2011 17th IEEE Real-Time and Embedded Technology and Applications Symposium
Real-time systems and applications are becoming increasingly complex and often comprise multiple communicating tasks. The management of the individual tasks is well-understood, but the interaction of communicating tasks with different timing characteristics is less well-understood. We discuss several representative inter-task communication flows via reserved memory buffers (possibly interconnected via a real-time network) and present RAD-Flows, a model for managing these interactions. We provide proofs and simulation results demonstrating the correctness and effectiveness of RAD-Flows, allowing system designers to determine the amount of memory required based upon the characteristics of the interacting tasks and to guarantee real-time operation of the system as a whole.
19th Euromicro Conference on Real-Time Systems (ECRTS'07), 2007
Dynamic memory storage has been widely used for years in computer science. However, its use in real-time systems has not been considered as an important issue, and memory management has not receive much consideration, whereas today's real-time applications are often characterized by highly fluctuating memory requirements. In this paper we present an approach to dynamic memory management for real-time systems. In response to application behavior and requests, the underlying memory management system adjusts resources to meet changing demands and user needs. The architectural framework that realizes this approach allows adaptive allocation of memory resources to applications involving both periodic or aperiodic tasks. Simulation results demonstrate the suitability of the proposed mechanism.
2012
Guaranteeing time-predictable execution in real-time systems involves the management of not only processors but also other supportive components such as cache memory, network on chip (NoC), memory controllers. These three components are designed to improve the system computational throughput through either bringing data closer to the processors (e.g cache memory) or maximizing concurrency in moving data inside the systems (e.g. NoC and memory controllers). We observe that these components can be sources of significant unpredictability in task executions if they are not operated in a deterministic manner. In particular, our analysis and experiments in [6, 35] show that with the standard cache and memory controller sharing mechanism, the execution time of a task may be unpredictably extended up to 33 to 44% in a single-core processor. We also show that analysis techniques and scheduling algorithms that have been proposed to account for and/or to mitigate this unpredictability often do not adequately address the problem at hand. As the consequence, those techniques and algorithms can only guarantee real-time execution in systems with under-utilized shared resources. In this dissertation, we study the software and hardware infrastructure, optimization techniques and scheduling algorithms that guarantee predictable execution in real-time systems that use cache memory, network on chip (NoC), and memory controllers. The main challenge is how to guarantee system predictability in such a way that maximizes the benefits and the utilization of these components. We achieve that by carefully analyzing both theoretical and practical assumptions in the use of these components and deriving novel solutions based on this understanding. For cache memory, we propose the use of softwarebased cache partitioning techniques and a real-time optimization method to minimize the system real-time utilization. The proposed solution renders better performance because of its fully utilization of available cache area. For NoC scheduling, we proposed novel scheduling algorithms that are designed to cope directly with the unique assumption on resource sharing in NoC. As will be shown, in practical systems, these scheduling algorithms can achieve near optimal performance.
Real-time systems and applications are becoming increasingly complex and larger, often requiring to process more data that what could be fitted in main memory. The management of the individual tasks is well-understood, but the interaction of communicating tasks with different timing characteristics is less well-understood. We discuss how to model prefetching across a series of real-time tasks/components communicating flows via reserved memory buffers (possibly interconnected via a real-time network) and present RAD-FETCH, a model for characterizing and managing these interactions. We provide proofs demonstrating the correctness RAD-FETCH, allowing system designers to determine the amount of memory required and latency bounds based upon the characteristics of the interacting real-time tasks and of the system as a whole.
Proceedings Design, Automation and Test in Europe, 1998
The demands in terms of processing performance, communication bandwidth and real-time throughput of many multimedia applications are much higher than today's processing architectures can deliver. The PROPHID heterogeneous multiprocessor architecture template aims to bridge this gap. The template contains a general purpose processor connected to a central bus, as well as several high-performance application domain specific processors. A high-throughput communication network is used to meet the high bandwidth requirements between these processors. In this network multiple time-division-multiplexed data streams are transferred over several parallel physical channels. This paper presents a method for guaranteeing the throughput for hard-real-time streams in such a network. At compile time sufficient bandwidth is assigned to these streams. The assignment can be determined in polynomial time. Remaining bandwidth is assigned to soft-real-time streams at run time. We thus achieve efficient stream communication with guaranteed performance.
1991
This paper investigates communication in distributed memory multiprocessors to support tasklevel parallelism for real-time applications. It is shown that wormhole routing, used in second generation multicomputers, does not support task-level pipelining because its oblivious contention resolution leads to output inconsistency in which a constant throughput is not guaranteed. We propose scheduled routing which guarantees constant throughputs by integrating task specifications with flow-control. In this routing technique, communication processors provide explicit flowcontrol by independently executing switching schedules computed at compile-time. It is deadlock-free, contention-free, does not load the intermediate node memory, and makes use of the multiple equivalent paths between non-adjacent nodes. The resource allocation and scheduling problems resulting from such routing are formulated and related implementation issues are anal yzed. A comparison with wormhole routing for various generalized hyp ercubes and tori shows that scheduled routing is effective in providing a constant throughput when wormhole routing does not and enables pipelining at higher input arrival rates.
ARTOSS
Resource Reservation (RR) is a class of real-time schedulers, proposed by the research community for hard and soft real-time systems, which are receiving considerable attention from industry. With this white paper, we would like to trigger a broad discussion between the academic and the industrial world on the use of RR techniques in standard operating systems. After presenting the major reasons for using RR ("why"), we present a set of propositions on "what" and "how" should be provided, which pinpoint the demands on operating systems and the research issues that remain to be addressed.
1997
Increases in processor speeds and the availability of audio and video devices for personal computers have encouraged the development of interactive multimedia applications for teleconferencing and digital audio/video presentation among others. These applications have stringent timing constraints, and traditional operating systems are not well suited to satisfying such constraints. On the other hand, hard real-time systems that can meet these constraints are typically static and inflexible. This dissertation presents an enforced operating system resource reservation model for the design and implementation of predictable real-time programs. Applications can reserve resources based on their timing constraints, and an enforcement mechanism ensures that they do not overrun their reservations. Thus, reserves isolate real-time applications from the temporal properties of other real-time (and non-real-time) applications just as virtual memory systems isolate applications from memory accesses by other applications. In addition, reserves are first class objects that are separated from control abstractions such as processes or threads. Therefore reserves can be passed between applications, and this model extends naturally to distributed systems. Reserves support the development of hard real-time and soft real-time programs, and programming techniques based on reserves illustrate how to use them effectively. An implementation of processor reserves in Real-Time Mach shows that reserved multimedia applications can achieve predictable real-time performance. vi vii Acknowledgments I would like to express my appreciation to my advisors, Mootaz Elnozahy and Raj Rajkumar, for their guidance, technical expertise, and time which they so generously shared with me during my doctoral studies. Thanks also to M. Satyanarayanan, Hide Tokuda, and Kevin Jeffay for their insights, critical comments, and encouragement. I am especially indebted to Hide Tokuda who was my mentor for several years before I entered the graduate program at CMU. Hide started the Real-Time Mach Project, which provided the research environment for this work, and Raj took over the project in the final years of my thesis work. I am indebted to both of them for their support. I would like to thank Jim Morris for his guidance and assistance. He helped me better understand how to do systems research and served as a role model for me. Thanks go to Roger Dannenberg for the opportunity to work with him and learn from him on several interesting computer music projects (and for the occasional trumpet duet and brass ensemble session). A special thanks to Joan Maddamma who looked out for me in many ways during my years at CMU. From the time I was an undergraduate through my years as a graduate student, Joan has been a very special friend. Many other people who I worked with over the years had a positive influence on me and on the work contained in this dissertation. I would like to thank Stefan Savage and Jim Zelenka for their help with pieces of the implementation of reserves in Real-Time Mach and for being good friends and colleagues. And I would like to thank
2003
When executing different real-time applications on a single processor system, one problem is how to compose these applications and guarantee at the same time that their timing requirements are not violated. A possible way of composing applications is through the resource reservation approach. Each application is handled by a dedicated server that is assigned a fraction of the processor. Using this approach, the system can be seen as a two-level hierarchical scheduler. A considerable amount of work has been recently addressed to the analysis of this kind of hierarchical systems. However, a question is still unanswered: given a set of real-time tasks to be handled by a server, how to assign the server parameters so that the task set is feasible? In this paper, we answer to the previous question for the case of fixed priority local scheduler by presenting a methodology for computing the class of server parameters that make the task set feasible.
Journal of Parallel and Distributed Computing, 1996
RealTimeTalk (RTT) is a design framework for developing distributed real-time applications with both hard and soft requirements. The framework supports design via hierarchical decomposition.
1996
The goal of the Rialto project at Microsoft Research is to build a system architecture supporting coexisting independent real-time (and non-real-time) programs. Unlike traditional embedded-systems real-time environments, where timing and resource analysis among competing tasks can be done off-line, it is our goal to allow multiple independently authored real-time applications with varying timing and resource requirements to dynamically coexist and cooperate to share the limited physical resources available to them, as well as also coexisting with nonreal-time applications.
2012
Mul ple programming models are emerging to address the increased need for dynamic task-level parallelism in applica ons for mul-core processors and shared-memory parallel compu ng, presen ng promising solu ons from a user-level perspec ve. Nonetheless, while high-level parallel languages offer a simple way for applica on programmers to specify parallelism in a form that easily scales with problem size, they s ll leave the actual scheduling of tasks to be performed at run me. Therefore, if the underlying system cannot efficiently map those tasks on the available cores, the benefits will be lost. This is par cularly important in modern real-me systems as their average workload is rapidly growing more parallel, complex and compu ng-intensive, whilst preserving stringent ming constraints. However, as the real-me scheduling theory has mostly been focused on sequen al task models, a shi to parallel task models introduces a completely new dimension to the scheduling problem. Within this context, the work presented in this thesis considers how to dynamically schedule highly heterogeneous parallel applica ons that require real-me performance guarantees on mul-core processors. A novel scheduling approach called RTWS is proposed. RTWS combines the G-EDF scheduler with a priority-aware work-stealing load balancing scheme, enabling parallel real-me tasks to be executed on more than one processor at a given me instant. Two stealing sub-policies have arisen from this proposal and their suitability is discussed in detail. Furthermore, this thesis describes the implementa on of a new scheduling class in the Linux kernel concerning RTWS, and extensively evaluate its feasibility. Experimental results demonstrate the greater scalability and lower scheduling overhead of the proposed approach, compara vely to an exis ng real-me deadline-driven scheduling policy for the Linux kernel, as well as reveal its be er performance when considering tasks with intra-task parallelism than without, even for short-living applica ons. We show that busy-aware stealing is robust to small devia ons from a strict priority schedule and conclude that some priority inversion may be actually acceptable, provided it helps reduce conten on, communica on, synchronisa on and coordina on between parallel threads.
18th Euromicro Conference on Real-Time Systems (ECRTS'06), 2000
As real-time and embedded systems become increasingly large and complex, the traditional strictly static approach to memory management begins to prove untenable. The challenge is to provide a dynamic memory model that guarantees tight and bounded time and space requirements without overburdening the developer with memory concerns. This paper provides an analysis of memory management approaches in order to characterise the tradeoffs across three semantic domains: space, time and a characterisation of memory usage information such as the lifetime of objects. A unified approach to distinguishing the merits of each memory model highlights the relationship across these three domains, thereby identifying the class of applications that benefit from targeting a particular model. Crucially, an initial investigation of this relationship identifies the direction future research must take in order to address the requirements of the next generation of complex embedded systems. Some initial suggestions are made in this regard and the memory model proposed in the Real-Time Specification for Java is evaluated in this context.
IEEE Transactions on Computers, 2004
In this paper, we present the BandWidth Inheritance (BWI) protocol, a new strategy for scheduling real-time tasks in dynamic systems, which extends the resource reservation framework to systems where tasks can interact through shared resources. The proposed protocol provides temporal isolation between independent groups of tasks and enables a schedulability analysis for guaranteeing the performance of hard real-time tasks. We show that BWI is the natural extension of the well-known Priority Inheritance Protocol to dynamic reservation systems. A formal analysis of the protocol is presented and a guarantee test for hard real-time tasks is proposed that takes into account the case in which hard real-time tasks interact with soft real-time tasks.
IFAC Proceedings Volumes, 1991
YARTOS is an experimental real-time operating system kernel that provides guaranteed response times to tasks. It is currently used as a vehicle for research in the design, analysis, and implementation of real-time applications. It is a micro-kernel with an underlying formal model based on sporadic tasks with response time requirements and shared software resources. It is distinguished by the programming model it supports and by its use of a novel processor scheduling and resource allocation policy. The implementation of YARTOS is outlined and two real-time applications that run under YARTOS are described.
10th IEEE International Symposium on Object and Component-Oriented Real-Time Distributed Computing (ISORC'07), 2007
Enabling message communication among concurrent computing threads without relying on mutual exclusion (i.e., locking) is highly desirable in real-time computing systems. This paper presents a refined version of the Non-Blocking Buffer (NBB), which is a lock-free interaction mechanism that enables efficient event-message communication between a single producer thread and a single consumer thread. The NBB scheme presented here contains improvements over the previous version in two aspects. First, application designers now have the flexibility of choosing the consumer's retry strategy for the case when the buffer is empty but the producer is in the middle of inserting an item. Second, in the refined version the producer inserts pointers to data items into the buffer whereas the consumer obtains copies of the items. This design is consistent with the fact that shared heap management must be avoided to enable fully lock-free interaction between the producer and the consumer. This paper also discusses the approaches based on the NBB mechanism for supporting all conceivable producer-consumer scenarios.
2012
Abstract Real-time scheduling of memory-intensive applications is a particularly difficult challenge. On a multi-core system, not only is the CPU scheduling an issue, but equally important is the management of mutual interference among tasks caused by simultaneous access to the shared main memory. To confront this problem, we explore real-time schedulers for task sets which adhere to the Predictable Execution Model (PREM).
Lecture Notes in Computer Science, 2002
Embedded systems comprise of tasks that have a wide variety of timing requirements, from the lax to the very stringent. The mixing of such tasks has been handled by specialized real-time schedulers, from the traditional cyclic executive dispatcher to sophisticated dynamic-priority schedulers. A common assumption of these real-time schedulers is the availability of global knowledge of the entire task set, and this assumption is required to ensure the schedulability of the timecritical tasks notwithstanding the interference of the less time-critical tasks. In this paper, we discuss the notion of a real-time virtual resource which abstracts the sharing of a physical resource such as a CPU by multiple time-critical tasks. Each real-time virtual resource is a virtual resource in the traditional sense of operating systems but its rate of service provision varies with time and is bounded. The real-time virtual resource abstraction allows tasks with wide-ranging timing criticality to be programmed as if they run on dedicated but slower CPUs such that global knowledge of the tasks is not necessary for schedulability analysis. More importantly, events or signals that are timing sensitive may retain their timeliness properties to within a bound under the real-time virtual resource abstraction, thereby permitting the composition of real-time tasks to preserve global timeliness properties.
2007
Cache memories are crucial to obtain high performance on contemporary computing systems. However, sometimes they have been avoided in real-time systems due to their lack of determinism. Unfortunately, most of the published techniques to attain predictability when using cache memories are complex to apply, precluding their use on real applications. This paper proposes a memory hierarchy such that, when combined with a careful pre-existing selection of the instruction cache contents, it brings an easy way to obtain predictable yet high-performance results. The purpose is to make possible the use of instruction caches in realistic realtime systems, with the ease of use in mind. The hierarchy is founded on a conventional instruction cache based scheme plus a simple memory assist, whose operation offers a very predictable behaviour and good performance thanks to the addition of a dedicated locking state memory. 1
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