Hardware-software codesign of embedded systems

ACM Transactions on Design Automation of Electronic Systems, 2000

The attempt to integrate the design tecnique of hardware and software is the aim of CoDesign. In this work, we present a CoDesign methodology based on a formal approach to embedded system speci cation. This methodology uses the Templated T-LOTOS language to specify the system during all the design phases. Templated T-LOTOS is a formal language based on CCS and CSP models. Using Templated T-LOTOS a system can be speci ed by observing the temporal ordering in which the events occur from the outside.

2005

The development of software for complex reactive embedded systems requires automated support for the verification of functional and non-functional properties. Currently, a language (or a design methodology) that can provide both at the same time without incurring in excessive inefficiencies is not available and separation of concerns is the solution advocated by many. Most research and commercial languages and tools focus on providing support for the design and validation of functional properties. At a different level, models and theory have been developed for supporting the description of the threads and resources composing the software architecture, and schedulability analysis provides support for the validation of timing constraints. However, the design of the concurrent structure of the application is still done manually. The system designer has to decide the number of threads, their structure and interactions, without the possibility of evaluating the trade-off between different solutions. This paper presents a solution towards what we believe to be a key objective, that is the synthesis of the architecture-level design and the automated logical-to-architectural mapping. Our proposal tries to reduce the overheads and excessive priority inversions of existing solutions that map all functional blocks (or reactions) into a single thread or assign a thread of execution to each action or possibly to each active object. After presenting our algorithm, we compare it with existing solutions and provide a schedulability analysis of the resulting system. Index Terms-Software models, architecture level design, scheduling, dynamic priorities.

Microporous and Mesoporous Materials, 2001

Abxrrucr-This article describes a new approach to hardwaresoftware codesign for complex embedded systems, using high-level programming languages, such as C, C++, Java, or Ada. Unlike previous approaches, we do not distribute parls of the behavior between the different subsystems. We map the entire behavior onto the whole system, and the partition is made implicitly during the synthesis process. We divide the system specification into behavior, architecture and design criteria, to maximize reuse opportunities and to increase the flexibility of the design environment.

12th IEEE International Conference on Embedded and Real-Time Computing Systems and Applications (RTCSA'06), 2006

Hardware/software codesign involves various design problems including system specification, design space exploration, hardware/software co-verification, and system synthesis. A codesign environment is a software tool that facilitates capabilities to solve these design problems. This paper presents the PeaCE codesign environment mainly targeting for multimedia applications with real-time constraints. PeaCE specifies the system behavior with a heterogeneous composition of three models of computation. The PeaCE environment provides seamless co-design flow from functional simulation to system synthesis, utilizing the features of the formal models maximally during the whole design process. Preliminary experiments with real examples prove the viability of the proposed technique.

Proceedings Ninth Annual IEEE International Conference and Workshop on the Engineering of Computer-Based Systems, 2000

Most current codesign approaches leverage from a complete specification of an application design at the implementation level. We pursue here an implementation independent system level design specification for realtime embedded systems using modular executable discrete event models. This paper introduces a formal abstraction for the specification of such design models. In addition, it defines a set of refinement steps which may be used to refine abstract design models into implementation level design specifications. Our approach is illustrated using a small embedded systems application.

Proceedings of 11th Euromicro Conference on Real-Time Systems. Euromicro RTS'99

Hardware-software codesign results of c~ncurrcnt embedded realtime systems are often not easily verifiable. The main difficulty lies in-the different timescales df the embedded hardware, of thk embedded software, and of the environment. This rate difference cawes state-space explosions and hence coverification has been mostly restricted t0 the initial system specifications. Currently, most codesign tools or methodologies only support validation in the form of cosimulation and testing. Here, we propose a new formal coverification method based on linear hybrid automam. The basic problems found in nm~t coveritication tasks are presented and solved. For complex systems, a simplification strategy is proposed to attack state-space explosions in formal covedtication. Experimental results show the feasibility of our approach and the increase in verification scalability through the application of the proposed method.

IEEE Transactions on Software Engineering, 2004

The growing complexity of embedded real-time software requirements calls for the design of reusable software components, the synthesis and generation of software code, and the automatic guarantee of nonfunctional properties such as performance, time constraints, reliability, and security. Available application frameworks targeted at the automatic design of embedded real-time software are poor in integrating functional and nonfunctional requirements. To bridge this gap, we reveal the design flow and the internal architecture of a newly proposed framework called Verifiable Embedded Real-Time Application Framework (VERTAF), which integrates software component-based reuse, formal synthesis, and formal verification. A formal UML-based embedded real-time object model is proposed for component reuse. Formal synthesis employs quasi-static and quasi-dynamic scheduling with automatic generation of multilayer portable efficient code. Formal verification integrates a model checker kernel from SGM, by adapting it for embedded software. The proposed architecture for VERTAF is component-based and allows plug-and-play for the scheduler and the verifier. Using VERTAF to develop application examples significantly reduced design effort and illustrated how high-level reuse of software components combined with automatic synthesis and verification can increase design productivity.

2001

The hardware-software codesign of distributed embedded systems is a more challenging task, because each phase of codesign, such as copartitioning, cosynthesis, cosimulation, and coverification must consider the physical restrictions imposed by the distributed characteristics of such systems. Distributed systems often contain several similar parts for which design reuse techniques can be applied. Object-oriented (OO) codesign approach, which allows physical restriction and object design reuse, is adopted in our newly proposed Distributed Embedded System Codesign (DESC) methodology. DESC methodology uses three types of models: Object Modeling Technique (OMT) models for system description and input, Linear Hybrid Automata (LHA) models for internal modeling and verification, and SES/workbench simulation models for performance evaluation. A two-level partitioning algorithm is proposed specifically for distributed systems. Software is synthesized by task scheduling and hardware is synthesized by system-level and object-oriented techniques. Design alternatives for synthesized hardware-software systems are then checked for design feasibility through rapid prototyping using hardware-software emulators. Through a case study on a Vehicle Parking Management System (VPMS), we depict each design phase of the DESC methodology to show benefits of OO codesign and the necessity of a two-level partitioning algorithm.

Proceedings EURO-DAC '96. European Design Automation Conference with EURO-VHDL '96 and Exhibition, 1996

In this paper, a design methodology for the design of microelectronic systems which includes hardware and software for open-loop and closed-loop control will be presented. An integrated approach to specification and design, analysis and simulation of the overall system has been developed. This provides for a systematic, computer aided approach to requirements definition, specification and design as well as verification and validation of the results. As embedded systems often require real-time capabilities, the environment presented gives special consideration to these constraints. We give an example for concrete applications, which shows, how the design of real-time embedded systems is supported by the design methodology and environment.

Lecture Notes in Computer Science, 2004

In this work, we propose a complete methodology called RESS (Real-Time Embedded Software Synthesis) for the automatic design of real-time embedded software. Several issues are solved, including software synthesis, software verification, code generation, graphic user interface, and system emulation. To avoid design errors, a formal approach is adopted because glitches in real-time embedded software are intolerable and very expensive or even impossible to fix. Time Complex-choice Petri Nets are used to model realtime embedded software, which are then synthesized using a time extended quasi static scheduling algorithm. The final generated C code is prototyped on an emulation platform, which consists of an 89C51 microcontroller for executing the software, an FPGA chip for programming the hardware for different applications, and some input/output devices. Two application examples are used to illustrate the feasibility of the RESS methodology.

1999

Abstract Software components for embedded reactive real-time applications must satisfy tight code size and run-time constraints. Cooperating finite state machines provide convenient intermediate format for embedded system co-synthesis, between high-level specification languages and software or hardware implementations. We propose a software generation methodology that takes advantage of a restricted class of specifications and allows for tight control over the implementation cost.

CRC Press eBooks, 2012

Currently available application frameworks that target the automatic design of real-time embedded software are poor in integrating functional and non-functional requirements for mobile and ubiquitous systems. In this work, we present the internal architecture and design flow of a newly proposed framework called Verifiable Embedded Real-Time Application Framework (VERTAF), which integrates three techniques namely software component-based reuse, formal synthesis, and formal verification. Component reuse is based on a formal unified modeling language (UML) real-time embedded object model. Formal synthesis employs quasi-static and quasi-dynamic scheduling with multi-layer portable efficient code generation, which can output either real-time operating systems (RTOS)-specific application code or automatically generated real-time executive with application code. Formal verification integrates a model checker kernel from state graph manipulators (SGM), by adapting it for embedded software. The proposed architecture for VERTAF is component-based which allows plug-and-play for the scheduler and the verifier. The architecture is also easily extensible because reusable hardware and software design components can be added. Application examples developed using VERTAF demonstrate significantly reduced relative design effort as compared to design without VERTAF, which also shows how high-level reuse of software components combined with automatic synthesis and verification increases design productivity.

2009

2004

Software synthesis is defined as the task of translating a specification into a software program, in a general purpose language, in such a way that this software can be compiled by conventional compilers. In general, complex real-time systems rely on specialized operating system kernels. However, the operating system usage may introduce significant overheads as in execution time as in memory requirement. In order to eliminate such overheads, automatic software synthesis methods should be implemented. Such methods comprise real-time operating system services (scheduling, resource management,communication, synchronization), and code generation. Formal methods are a very promising alternative to deal with the complexity of embedded systems, and for improving the degree of confidence in critical systems. We present a formal approach for automatic embedded hard real-time software synthesis based on time Petri nets. In order to illustrate the practical usability of the proposed method, it is shown how to synthesize a C code implementation using a heated-humidifier case study.

Proceedings of the 14th international ACM Sigsoft symposium on Component based software engineering - CBSE '11, 2011

To take advantage of component-based software engineering, software designers need a component framework that automates the assemblage and integration of developed components. It is then of prime importance to ensure that the synthesized code respects the definition of the component model's semantics. This is all the more difficult in the domain of embedded systems since the considered semantics usually aims at characterizing both functional properties (e.g. data and control dependencies) and non-functional properties such as timing and memory consumption. The component model considered in this paper, called ProCom, relies on an asynchronous operational semantics and a formal hypothesis of atomic and instantaneous interactions between components. The asynchronous approach targets higher flexibility in the deployment and analysis process, while the formal hypothesis helps in reducing the combinatory problems of formal verification. In this paper, we present a code generation strategy to synthesize ProCom components, and a formalization of this generated code. This formalization extends the verification possibilities of ProCom architectures, and constitutes a step toward the verification that the produced code respects the operational semantics of ProCom.