Compact and complete test set generation for multiple stuck-faults
Alberto Sangiovanni Vincentelli1997
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Abstract
Abstract We propose a novel procedure for testing all multiple stuck-faults in a logic circuit using two complementary algorithms. The first algorithm finds pairs of input vectors to detect the occurrence of target single stuck-faults independent of the occurrence of other faults. The second uses a sophisticated branch and bound procedure to complete the test set generation on the faults undetected by the first algorithm. The technique is complete and applies to all circuits.
Key takeaways
- We will also show h o w t o a c hieve signicant bounding in the enumeration of multiple faults when a multiple fault is detectable (but does not have an irrepressible component fault).
- Consider a SA-0 fault on the output of gate g5 in the circuit of Figure 1.
- The two cases shown on the top occur if neither fault on the AND gate can occur, i.e. these faults are irrepressible and have already been detected.
- While undetectable faults obviously do not contribute vectors to the complete test set, we m ust include vectors in the test set that detect all detectable multiple stuck-faults for which n o component fault can be provided with irrepressible detection.
- For most of the circuits, all single faults are irrepressible and hence all multiple stuck-faults are detected.
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