Towards Real-time Neuronal Disparity Map Estimation

Pattern Recognition, 2012

We propose in this paper a new method for real-time dense disparity map computing using a stereo pair of rectified images. Based on the neural network and Disparity Space Image (DSI) data structure, the disparity map computing consists of two main steps: initial disparity map estimation by combining the neuronal network and the DSI structure, and its refinement. Four improvements are introduced so that an accurate and fast result will be reached. The first one concerns the proposition of a new strategy in order to optimize the computation time of the initial disparity map. In the second one, a specific treatment is proposed in order to obtain more accurate disparity for the neighboring pixels to boundaries. The third one, it concerns the pixel similarity measure for matching score computation and it consists of using in addition to the traditional pixel intensities, the magnitude and orientation of the gradients providing more accuracy. Finally, the processing time of the method has been decreased consequently to our implementation of some critical steps on FPGAs. Experimental results on real datasets are conducted and a comparative evaluation of the obtained results relative to the state-of-art methods is presented.

International Arab Journal of Information Technology

In this paper, we propose a new approach of dense disparity map computing based on the neural network from a pair of stereo images. Our approach divides the disparity map computing into two main steps. The first one deals with computing the initial disparity map using a neuronal method (BP). Whereas the second one presents a very simple and faster method to refine the initial disparity map using image segmentation so an accurate result can be acquired. Experimental results on real data sets were conducted for evaluating the proposed method.

2009

Abstract: In this paper, we propose a new approach of dense disparity map computing based on the neural network from pair of stereo images. Our approach divides the disparity map computing into two main steps. The first one deals with computing the initial disparity map using a neuronal method Back-Propagation (BP). The BP network, using differential features as input training data can learn the functional relationship between differential features and the matching degree. Whereas, the second one presents a very simple and fast method to refine the initial disparity map by using image segmentation so an accurate result can be acquired. Experimental results on real data sets were conducted for evaluating the neural model proposed.

2010 International Conference on Machine and Web Intelligence, 2010

This work aims at defining a new approach for a dense disparity map computing based on the neural networks from a pair of stereo images. Our approach has been divided into two main tasks. The first one deals with computing the initial disparity map using a neuronal method (BP). Whereas the second one presents a simple method to refine the initial disparity map using neural refinement so that an accurate result can be acquired. In the literature, the matching score is based only on the pixel intensities. We introduce in this work two additional features: the gradient magnitude and orientation of the gradient vector of pixels which gives a true degree of similarity between pixels. Experimental results on real data sets were conducted for evaluating the proposed method.

Microprocessors and Microsystems, 2012

Several applications demand efficient hardware implementations of stereo vision systems in order to furnish real time three-dimensional measurements. This paper proposes a complete fast low-cost stereo vision system that performs stereo image rectification with tangential and radial distortion removal, computes dense disparity maps using the Sum of Absolute Differences as the dissimilarity metric, and, finally, exploits a novel injective consistency check purpose-designed for eliminating unreliable disparity values. The proposed system has been realized and hardware tested for several images resolutions and disparity ranges. When 1280 Â 720 grayscale images are processed with the disparity range equal to 30, the system allows a frame rate up to 97 fps@89 MHz to be reached. It has been realized on a single low-cost XilinxVirtex-4 XC4VLX60 FPGA chip and it occupies 63 DSPs, 128 BRAMs and 15728 slices.

Proceedings XXV Conference on Design of Circuits and Integrated Systems (DCIS 2010), 2010

Real-time stereo image matching is an important computer vision task. This paper presents the architecture and implementation of an FPGA-based stereo image processor, that produces 25 dense depth maps per second from pairs of 8-bit-per-pixel gray-scale images. The system implements a modification of a previously-reported variable-window-size method to determine the best correspondence for each image pixel. The degree of parallelism of the implementation can be adapted to the available resources: increased parallelism enables the processing of larger images (at the same frame rate). The proposed architecture exploits the memory resources available in modern platform FPGAs. Two prototype implementations have been produced and validated: the smaller one can handle pairs of images of size 208x480 , while the larger one works for images of size 640x480 (both operate at 100 MHz). These results improve on previously-reported ASIC and FPGA-based designs.

Microprocessors and Microsystems, 2008

Stereo vision deals with images acquired by a stereo camera setup, where the disparity between the stereo images allows depth estimation within a scene. 3D information, hence, is retrieved which is essential in many machine vision applications. Disparity map extraction of an image is a computationally demanding task. Previous work on disparity map computation is mainly limited to software based techniques on general-purpose architectures. In this paper a new hardware-efficient real-time disparity map computation module is developed. This enables a hardware-based cellular automata (CA) parallel-pipelined design, for the overall module, realized on a single FPGA device, the typical operating frequency of which is 256 MHz. Accurate disparity maps are computed at a rate of nearly 275 per second, for a stereo image pair with a disparity range of 80 pixels and 640 × 480 pixels spatial resolution. The presented hardware-based algorithm provides very good processing speed at the expense of accuracy, with very good scalability in terms of disparity levels. The proposed method allows the fastest disparity map computational module to be built, to the best of the authors’ knowledge so far, enabling a suitable module for real-time stereo vision applications.

Journal of Sensors, 2016

This paper presents a literature survey on existing disparity map algorithms. It focuses on four main stages of processing as proposed by Scharstein and Szeliski in a taxonomy and evaluation of dense two-frame stereo correspondence algorithms performed in 2002. To assist future researchers in developing their own stereo matching algorithms, a summary of the existing algorithms developed for every stage of processing is also provided. The survey also notes the implementation of previous software-based and hardware-based algorithms. Generally, the main processing module for a software-based implementation uses only a central processing unit. By contrast, a hardware-based implementation requires one or more additional processors for its processing module, such as graphical processing unit or a field programmable gate array. This literature survey also presents a method of qualitative measurement that is widely used by researchers in the area of stereo vision disparity mappings.

This paper describes an FPGA Correlation-Edge Distance approach for real time disparity map generation in stereo-vision. The proposed method calculates the disparity map for the input and disparity map for Edge Distance images of a stereopair. In both cases the approximation algorithm of disparity map SAD (Sum of Absolute Differences) is used. The final disparity map is determined from the previously generated maps, considering a homogeneity parameter defined for each point in the scene. Due to low complexity when implementing stereo vision algorithms in FPGA devices, the proposed method was implemented in a Cyclone II EP2C35F672C6 FPGA assembled in an Altera DE2 breadboard. The developed module can process stereo-pairs of 1280x1024 pixel resolution at a rate of 75 frames/s and produces 8-bit dense disparity maps within a range of disparities up to 63 pixels. The presented architecture provides a significant improvement in regions with uniformed texture over correlation based stereo-vision algorithms in the reported literature and an accelerated processing rate.

2018

It is evident that the accuracy of stereo matching algorithms has continued to increase, based on quantitative evaluations of the resulting disparity maps. Today a number of stereo matching algorithms are available to compute disparity maps. These algorithms are mainly classified as Local and Global algorithms. This paper focuses on designing a system for the estimation of disparity map using a simulation tool with the help of Local stereo matching algorithm. Here the designed system first extract corner feature from input side stereo image pair, then a fundamental matrix is calculated to get an epi polar geometry of a stereo image pair. Using epipoalar geometry, SSD and sub pixel accuracy distance between best similar points is calculated. Finally using this distances Disparity map is estimated. The system gives good disparity results within lesser time.