A novel genetic algorithm for evolvable hardware

2000

In the last decade there has been interest and research in the area of designing circuits with genetic algorithms, evolutionary algorithms, and genetic programming. However, the ability to design circuits of the size and complexity required by modern engineering design problems, simply by specifying required outputs for given inputs has as yet eluded researchers. This paper describes current research in the area of designing logic circuits using an evolutionary algorithm. The goal of the research is to improve the effectiveness of this method and make it a practical aid for design engineers. A novel method of implementing the algorithm is introduced, and results are presented for various multiprocessing systems. In addition to evolving standard arithmetic circuits, work in the area of evolving circuits that perform digital signal processing tasks is described.

International Journal of …, 2005

Evolvable hardware (EHW) is a developing field that applies evolutionary algorithm (EA) to automatically design circuits, antennas, robot controllers etc. A lot of research has been done in this area and several different EAs have been introduced to tackle numerous problems, as scalability, evolvability etc. However every time a specific EA is chosen for solving a particular task, all its components, such as population size, initialization, selection mechanism, mutation rate, and genetic operators, should be selected in order to achieve the best results. In the last three decade the selection of the right parameters for the EA's components for solving different "test-problems" has been investigated. In this paper the behaviour of mutation rate for designing logic circuits, which has not been done before, has been deeply analyzed. The mutation rate for an EHW system modifies the number of inputs of each logic gates, the functionality (for example from AND to NOR) and the connectivity between logic gates. The behaviour of the mutation has been analyzed based on the number of generations, genotype redundancy and number of logic gates for the evolved circuits. The experimental results found provide the behaviour of the mutation rate during evolution for the design and optimization of simple logic circuits. The experimental results propose the best mutation rate to be used for designing combinational logic circuits. The research presented is particular important for those who would like to implement a dynamic mutation rate inside the evolutionary algorithm for evolving digital circuits. The researches on the mutation rate during the last 40 years are also summarized.

2005 Nasa/DoD Conference on Evolvable Hardware (EH-2005), Proceedings, 2005

Evolvable hardware (EHW) [1] is a technique introduced to automatically design circuits where the circuit configuration is carried out by evolutionary algorithms. One of the main difficulties in using EHW to solve real-world problems is the scalability. Until now, several strategies have been proposed to avoid this problem, but none of them completely tackle the issue. In this paper three different methods for evolving the most complex circuits have been tested for their scalability. These methods are Bi-directional incremental evolution (SO-BIE)

The evolution of logic circuits, which falls under the heading of evolvable hardware, is carried out by evolutionary algorithms. These algorithms are able to automatically configure reconfigurable devices. One of main difficulties in developing evolvable hardware with the ability to design functional electrical circuits is to choose the most favourable EA features such as fitness function, chromosome representations, population size, genetic operators and individual selection. Until now several researchers from the evolvable hardware community have used and tuned these parameters and various rules on how to select the value of a particular parameter have been proposed. However, to date, no one has presented a study regarding the size of the chromosome representation (circuit layout) to be used as a platform for the evolution in order to increase the evolvability, reduce the number of generations and optimize the digital logic circuits through reducing the number of logic gates. In this paper this topic has been thoroughly investigated and the optimal parameters for these EA features have been proposed. The evolution of logic circuits has been carried out by an extrinsic evolvable hardware system which uses (1+λ) evolution strategy as the core of the evolution.

Proceedings of the 1998 ACM/SIGDA sixth international symposium on Field programmable gate arrays - FPGA '98, 1998

This paper describes how the massive parallelism of the rapidly reconfigurable Xilinx XC6216 FPGA (in conjunction with Virtual Computing's H.O.T. Works board) can be exploited to accelerate the time-consuming fitness measurement task of genetic algorithms and genetic programming. This acceleration is accomplished by embodying each individual of the evolving population into hardware in order to perform the fitness measurement task. A 16-step sorting network for seven items was evolved that has two fewer steps than the sorting network described in the 1962 O'Connor and Nelson patent on sorting networks (and the same number of steps as a 7sorter that was devised by Floyd and Knuth subsequent to the patent and that is now known to be minimal). Other minimal sorters have been evolved.

2000

An evolutionary algorithm is used as an engine for discovering new designs of digital circuits, particularly arithmetic functions. These designs are often radically different from those produced by top-down, human, rule-based approaches. It is argued that by studying evolved designs of gradually increasing scale, one might be able to discern new, efficient, and generalizable principles of design. The ripple-carry adder principle is one such principle that can be inferred from evolved designs for one and two-bit adders. Novel evolved designs for three-bit binary multipliers are given that are 20% more Ž . efficient in terms of number of two-input gates used than the most efficient known conventional design.

2015

The paper aims to provide an idea of the genetic algorithm parameters and its importance in the evolution of circuits through embedded evolvable hardware. Evolvable Hardware is an integration of evolutionary algorithms with programmable devices. A Genetic Algorithm fused into the soft processor of a Field Programmable Gate Array is termed, Evolvable Embedded Hardware. The system has the ability to converge to a solution faster due to the evaluation in a single device, when compared to the conventional evolvable hardware structure. An insight into the genetic algorithm and optimization of genetic parameters for design of combinational circuits is discussed. An experimental model for a 2 bit adder for different genetic parameters is validated to demonstrate the systematic evolution of evolvable embedded system hardware. This experimental setup is carried out on Virtex 6 (XC6VLX240T-1FFG1156) ML605 Evaluation Kit FPGA using the Xilinx Platform Studio 14.6 tools.

Genetic Programming and Evolvable Machines, 2000

In this paper an approach based on an evolutionary algorithm to design synchronous sequential logic circuits with minimum number of logic gates is suggested. The proposed method consists of four main stages. The first stage is concerned with the use of genetic algorithms (GA) for the state assignment problem to compute optimal binary codes for each symbolic state and construct the state transition table of finite state machine (FSM). The second stage defines the subcircuits required to achieve the desired functionality. The third stage evaluates the subcircuits using extrinsic Evolvable Hardware (EHW). During the fourth stage, the final circuit is assembled. The obtained results compare favourably against those produced by manual methods and other methods based on heuristic techniques.

Proceedings 2002 NASA/DoD Conference on Evolvable Hardware

The purpose of this paper is mofold: first, to illustrate a stand-alone board-level evolvable system (SABLES) and its performunee, and second to illustrate some problems that occur during evolution with real hardware in the loop, or when the intention of the user is not completely reflected in the fitness function. SABLES is part of an effort to achieve integrated evolvable systems. SABLES provides autonomous, fast (tens to hundreds of seconds), on-chip evolution involving about lO0,OOO circuit evaluations. Its main components are a JPL Field Programmable Transistor Array (FPTA) chip used as transistor-level reconfigurable hardware, and a TI DSP that implements the evolutionary algorithm controlling the FPTA reconfiguration. The paper details an example of evolution on SABLES and points out to certain transient and memory effects that affect the stability of solutions obtained reusing the same piece of hardware for rapid testing of individuals during evolution. It also illustrates how specifications not completely reflected in the fitness function, such as the time scales of response for logical circuits, m a y lead to overall unsatisfactory solutions. Both such situations can be handled with appropriate modification of fitness function and additional testing.

2008 4th Southern Conference on Programmable Logic, 2008

Traditional genetic algorithms require a lot of memory and processing power on embedded logic projects. Representing populations of candidate solutions through vectors of probabilities rather than sets of bit strings saves memory and processing. The compact genetic algorithm (CGA) is a probability vector based genetic algorithm. The article presents an FPGA implementation of the standard compact genetic algorithm with a few changes to improve search power. A data flow and a block diagram design are shown and described in the paper. Results demonstrate the requirements (logical blocks) needed for implementation, the architecture processing speed and the solving power of the CGA for evolvable hardware.

2003

The paper presents a Fielri Programmable Transistor Array (FPTA), developed as an experimental platform for implementing flexible, reconjigurable amlog computing. Parasitic effects of impedect switches interconnecting transistors deteriorate the pedormance of conventional designs when mapped to the FPTA. However, working design solutwns can be obkained through a search procedure guided by evolutionary algorithms. An example of evolutionary design is illustrated using a stand-alone boardlevel evolvable system (SABLES) in which the evolutionary algorithm is implemented with a DSP. SABLES can automatically configure the FPTA in tens to hundreds of seconds, time in which evaluates-100,OOO circuit candidate solutions. The paper details several examples of evolutionary synthesis of analog circuits on the FPTA. Evolved circuits include rectifier circuits, reconfigurable amlog filters and reconfigurable fizzy logic circuits.

Evolvable hardware (EHW) refers to a selfreconfiguration hardware design, where the configuration is under the control of an evolutionary algorithm (EA). A lot of research has been done in this area several different EA have been introduced. Every time a specific EA is chosen for solving a particular problem, all its components, such as population size, initialization, selection mechanism, mutation rate, and genetic operators, should be selected in order to achieve the best results. In the last three decade a lot of research has been carried out in order to identify the best parameters for the EA's components for different "test-problems". However different researchers propose different solutions. In this paper the behaviour of mutation rate on (1+λ) evolution strategy (ES) for designing logic circuits, which has not been done before, has been deeply analyzed. The mutation rate for an EHW system modifies values of the logic cell inputs, the cell type (for example from AND to NOR) and the circuit output. The behaviour of the mutation has been analyzed based on the number of generations, genotype redundancy and number of logic gates used for the evolved circuits. The experimental results found provide the behaviour of the mutation rate to be used during evolution for the design and optimization of logic circuits. The researches on the best mutation rate during the last 40 years are also summarized.

Proceedings - 2010 International Conference on Reconfigurable Computing and FPGAs, ReConFig 2010, 2010

Operating in critical environments is an extremely desired feature for fault-tolerant embedded systems. In addition, due to design test and validation complexity of these systems, faster and easier development methods are needed. Evolvable Hardware (EHW) is a development technique that, using reconfigurable hardware, builds systems that reconfiguration part is under the control of an Evolutionary Algorithm. Reconfigurable hardware allows EHW to change its own hardware structure adapting itself to task and/or environment changes. Evolvable part of these systems can also be implemented using Artificial Neural Networks (ANNs). This research work presents results and comparisons between Genetic Algorithm (GA) and ANN implementations that receive combinational circuits' truth-tables as input and searches the minimum circuit respecting this input truth-table. GA improved for this work's EHW structure achieve good execution time for tested tables and ANN modeling presents some non-desired characteristics with bad results.

Journal of AI and Data Mining, 2018

Usually, important parameters in the design and implementation of combinational logic circuits are the number of gates, transistors, and the levels used in the design of the circuit. In this regard, various evolutionary paradigms with different competency have recently been introduced. However, while being advantageous, evolutionary paradigms also have some limitations including: a) lack of confidence in reaching at the correct answer, b) long convergence time, and c) restriction on the tests performed with higher number of input variables. In this paper, we have implemented a genetic programming approach that given a Boolean function, outputs its equivalent circuit such that the truth table is covered and the minimum number of gates (and to some extent transistors and levels) are used. Furthermore, our implementation improves the aforementioned limitations by: Incorporating a self-repairing feature (improving limitation a); Efficient use of the conceivable coding space of the probl...

1997

This paper describes work which attempts to evolve circuit solutions for combinational logic systems directly onto Xilinx 6000 FPGA parts. The reason for attempting to evolve designs direct onto the device is twofold: (i) every circuit has a known functionality and (ii) every circuit must be able to be placed on the chip and then routed. Using evolutionary techniques allows us to consider these two important aspects of design and implementation as a single problem. The paper describes the basic method adopted, using a network list (netlist) chromosome and genes which represent circuit module function, and then discusses some of the results achieved, plus difficulties encountered, and some of the additional problems which still require to be solved in this new and exciting area of research.