A Fast Concurrent Power-Thermal Model for Sub-100nm Digital ICs

Journal of Low Power Electronics, 2011

Thermal (side-)effects can detrimentally influence operation of integrated circuits. The increase of temperature changes the devices' characteristics and may result in timing integrity issues. In extreme cases the increased delays can foil correct operation of the circuit. This paper presents a methodology as well as a tool to address timing integrity errors caused by thermal effects. The methodology presented shows how the thermal distribution map on the IC surface can be used to calculate device delay changes during logic simulation. A software tool called CellTherm developed in the Department of Electron Devices, BME, Hungary is also briefly presented in this paper. With the help of the software, logic simulations of digital integrated circuits can be back-annotated with temperaturedependent delays during the running simulation.

International Symposium on Low Power Electronics and Design, 1996

Transistor-level power simulators, which are more accurate than logic-level power estimators, have been popularly used to estimate the power dissipation of CMOS circuits. In this paper, we introduce a method which extends the Monte-Carlo approach for deriving the average power dissipation of a circuit using transistor-level power simulators. To reduce the simulation time, we propose a mixedlevel extrapolation technique to speed up the convergence rate of the process, and thereby to achieve a good balance between simulation time and accuracy. Experimental results show that this is a promising method for deriving the accurate power dissipation of a circuit within reasonable time budget.

Proceedings of 1996 International Symposium on Low Power Electronics and Design, 1996

Transistor-level power simulators, which are more accurate than logic-level power estimators, have been popularly used to estimate the power dissipation of CMOS circuits. In this paper, we introduce a method which extends the Monte-Carlo approach for deriving the average power dissipation of a circuit using transistor-level power simulators. To reduce the simulation time, we propose a mixedlevel extrapolation technique to speed up the convergence rate of the process, and thereby to achieve a good balance between simulation time and accuracy. Experimental results show that this is a promising method for deriving the accurate power dissipation of a circuit within reasonable time budget.

2014 International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS XIV), 2014

We introduce and experimentally validate a new macro-level model of the CPU temperature/power relationship within nanometer-scale application processors or system-onchips. By adopting a holistic view, this model is able to take into account many of the physical effects that occur within such systems. Together with two algorithms described in the paper, our results can be used, for instance by engineers designing power or thermal management units, to cancel the temperatureinduced bias on power measurements. This will help them gather temperature-neutral power data while running multiple instance of their benchmarks. Also power requirements and system failure rates can be decreased by controlling the CPU's thermal behavior.

Evolutionary Intelligence, 2020

Designing a typical microcircuit for multi-core chips includes the development of the overall system architecture as well as the creation of single-chip multiprocessor systems, which house a set of interrelated nodes. To evaluate the complexity and power consumption of these multiprocessor systems, adequate models and methods are required. A simplified model for calculating heat dissipation in conductors suits this purpose completely. The preliminary settlement of the heat dissipation parameter will allow engineers to evaluate the on-chip interconnect topology at the early stages of design so that these interconnects comply with the power dissipation and the power consumption variables. The novelty of this approach lies in the fact that it allows modeling thermal stresses that take place inside the chip. A solver applied here enables numerical solution to differential equations that is theoretically best, i.e., a direct numerical solution. In addition, it overcame the Gibbs phenomenon by incorporating more natural, not sharp boundary conditions into the model. Here, this approach was applied to the multiprocessor system design that implies the integration of processor cores in a single chip package.

IEEE Transactions on Electron Devices, 2000

As transistors continue to evolve along Moore's Law and silicon devices take advantage of this evolution to offer increasing performance, there is a critical need to accurately estimate the silicon-substrate (junction or die) thermal gradients and temperature profile for the development and thermal management of future generations of all high-performance integrated circuits (ICs) including microprocessors. This paper presents an accurate chip-level leakage-aware method that self-consistently incorporates various electrothermal couplings between chip power, junction temperature, operating frequency, and supply voltage for substrate thermal profile estimation and also employs a realistic package thermal model that comprehends different packaging layers and noncubic structure of the package, which are not accounted for in traditional analyses. The evaluation using the proposed methodology is efficient and shows excellent agreements with an industrial-quality computational-fluid-dynamics (CFD) based commercial software. Furthermore, the methodology is shown to become increasingly effective with increase in leakage as technology scales. It is shown that considering electrothermal couplings and realistic package thermal model not only improves the accuracy of estimating the heat distribution across the chip but also has significant implications for precise power estimation and thermal management in nanometer-scale CMOS technologies.

This paper introduces a new approach to pattern dependent static power estimation in logic blocks, which are realized 'on-the-fly' in a library-free design environment. A static current model is first developed at the transistor level and then extended to the logic gate level and finally the logic block level. For varying transistors widths and input stimuli, the transistor level model has performed with good accuracy compared to SPICE for technologies ranging from 65nm down to 32nm. The gate level model is pattern dependent and deals with basic gates and complex gates. A transistor collapsing scheme was developed to achieve simpler structure leading to analytical models with high computational efficiency and good accuracy ranging from 0.1-5.4% for basic logic gates and 3.7-6.2% for complex gates. Using these static current estimation models, a methodology has been introduced to estimate static power dissipation of logic blocks in a library-free design environment, in which the cells are generated and sized 'on-the-fly' driven by specification and targeted technology. Across several MCNC benchmarks, the estimation methodology proposed exhibits a worst case mean percentage error of 1.1% compared to SPICE. It also exhibits runtime that is on average 43 times faster than SPICE.

2002

As the feature size decrease with each process generation, and nominal SoC design size approaching millions of gates, there is a need to explore more in depth the power distribution across the IC and investigate the power planning and thermal effects on the functionality and reliability. We propose in this paper a methodology that allows computing the local power of a digital circuit mapped to the physical representation in order to analyze the power distribution. This is used as inputs to a thermal simulator for extracting the thermal maps of the chip. The power calculation cannot be done at the transistor level for multi-million transistors with large test-benches, otherwise it will need unreasonable CPU resources and memory. This is why the proposed method is based on the digital model, as it is used currently in industry for functional and timing simulations sign-off. The obtained thermal results are accurate accordingly. And this allows both quantitative and qualitative analysis of the thermal behavior under real application inside the circuit.

2018 28th International Symposium on Power and Timing Modeling, Optimization and Simulation (PATMOS), 2018

While state-of-the-art system-level simulators can deliver swift estimation of power dissipation for microprocessor designs, they do so at the expense of reduced accuracy. On the other hand, RTL simulators are typically cycle-accurate but overwhelmingly time consuming for real-life workloads. Consequently, the design community often has to make a compromise between accuracy and speed. In this work, we propose a novel cross-layer approach that can enable accurate power estimation by carefully integrating components from system-level and RTL simulation of the target design. We first leverage the concept of simulation points to transform the workload application and isolate its most critical segments. We then profile the highest weighted simulation point (HWSP) with a RTL simulator (AnyCore) for maximum accuracy, while the rest are simulated with a system-level simulator (gem5) for ensuring fast evaluation. Finally, we combine the integrated set of profiling data as input to the power simulator (McPAT). Our evaluation results for three different SPEC2006 benchmark applications demonstrate that our proposed crosslayer framework can improve the power estimation accuracy by up to 15% for individual simulation points and by ∼9% for the full application, compared to that of a conventional system-level simulation scheme.

2007

In this paper, we present a new technique to calculate the power dissipation profile from the IC temperature map using an analogy with image processing and restoration. In this technique, finite element analysis (FEA) is used to find the heat point spread function of the IC chip. Then, the temperature map is used as input for an efficient image restoration algorithm which locates the sources of strong power dissipation non-uniformities. Therefore, for the first time we optimally solve the inverse heat transfer problem, and estimate the IC power map without involving extensive lab experiments. Our computationally efficient and robust method, unlike some previous techniques in the literature, is applicable to virtually any experimental scenario. Simulation results on a typical commercial IC device confirm the effectiveness of our proposed method.

1999

This paper presents a efficient approach for the estimation of signal activity figures based on a gate level description of a digital circuit. Exploiting an event oriented simulation system a methodology for calculating very accurate power estimates for digital circuits is presented. A calibration scheme for characterizing the power dissipation of logic gates based on a few key parameters will be outlined. The proposed method proves that the use of an event oriented simulation system calibrated with these gate specific parameters allows power estimations which are comparable to transistor level (SPICE) simulation accuracy. This is essential for the analysis of large circuits, because the proposed event driven simulation system is about 10000 times faster than transistor level simul ation. Experimental results and benchmarks are presented which demonstrates significant improvements in terms of performance, accuracy and flexibility of this approach compared to other state of the art power estimation met hods.

Proceedings of the 2005 international symposium on Low power electronics and design - ISLPED '05, 2005

Modeling and analyzing detailed die temperature with a full-chip thermal model at early design stages is important to discover and avoid potential thermal hazards. However, omitting important aspects of package details in a thermal model can result in significant temperature estimation errors. In this paper, we discuss the applications of an existing compact thermal model that models both die and package temperature details. As an example, a thermally selfconsistent leakage power calculation of a POWER4-like microprocessor design is presented. We then demonstrate the importance of including detailed package information in the thermal model by several examples considering the impact of thermal interface material (TIM), which glues the die to the heat spreader. The fact that detailed package information is needed to build an accurate compact thermal model implies a design flow, in which the chip-and package-level compact thermal model acts as a convenient medium for more productive collaborations among circuit designers, computer architects and package designers, leading to early and efficient evaluations of different design tradeoffs for an optimal design from a thermal point of view.

Evaluating Cache Power Dissipation Across Different Process Technologies, 2018

Dynamic power dissipation due to signal transitions is the primary power dissipation source, while static power will become increasingly significant in upcoming processors. Dynamic power is directly related to the activity of the circuits, and static power depends on the amount of powered-on transistors and their physical characteristics. Thus, large circuits are usually the primary source of static power. Caches are generally the largest structures in the processor, so they are the most important sources of the static power dissipation. It is also known that increasing cache associativity and/or size to reduce the miss ratio and enhance the performance has an impact on static power and access time. On the other hand, a low access time is desired for the performance. Power and performance also depend on the number of cache ports. In this paper, CACTI 6.0 is used to evaluate cache power dissipation combined with nanometer models of various cache configurations. Cache power dissipation is focused on to show how much power cache consumes, and what fraction can be attributed to dynamic (switching) and static (leakage) currents. Where chip fabrication technology shrank from 130nm to 32nm over the last decade, in this paper, we explore a three-dimensional cache design space by studying caches with different sizes (32kB to 256kB), associativity (direct-mapped to 16-way) and process technologies (90nm, 65nm, 45nm, and 32nm).

Lecture Notes in Computer Science, 2009

Power modeling techniques have traditionally neglected the main part of the energy consumed in the internal nodes of static CMOS gates: the power dissipated by input transitions that do not produce output switching. In this work, we present an experimental setup that shows that this power component may contribute up to 59% of the total power consumption of a gate in modern technologies. This fact makes very important to include it into any accurate power model. 1

The Journal of King Mongkut's University of Technology North Bangkok, 2017

The continued scaling of semiconductor technologies leads to diverse challenges such as power and temperature, which also forces reliability as another design metric of prime concern. There exists strong need to link reliability with physical metrics in a high-level architecture design environment, where estimation of reliability impacts can be performed in the early design stage. In this paper, we propose a joint modeling and simulation framework for power, thermal and timing variation, which is integrated into a commercial high-level processor design environment. A custom timing variation model is provided for estimation of dynamic timing variation, which is demonstrated using one nanoscale thermal effect known as Inverted Temperature Dependence. The complete modeling flow is automated for customized processor model with arbitrary architectural hierarchy, which assists designer to perform architectural and application-level design space exploration with power, thermal and reliability impacts.