Operating-system controlled network on chip

Microprocessors and Microsystems, 2017

We present a novel network-on-chip (NoC) architecture, called SDNoC, that is based on a hybrid hardware/software approach. This approach is based on a few principles used in Software Defined Networks (SDNs). In particular, the control network and the data network are physically separated. In addition, SDNoC is controlled by a centralized Network Manager (NM) implemented in software that is executed on a dedicated core. These principles lead to many advantages. 1) Computation of paths is simple and the allocation of routes is efficient because the NM has a global view. Moreover, the NM is not limited to a small set of allowed routes and can easily deal with unexpected irregular traffic patterns. 2) The switches that forward phits in SDNoC are simple because they are configured by the NM, do not store phits, and do not have routing tables. 3) The overhead consumed by packet headers/trailers and control messages is greatly reduced. 4) There is no need for a complicated error-prone distributed protocol that avoids deadlock, starvation, etc. 5) Power consumption is proportional to the traffic in the NoC (as the NM processes requests, and the switches forward incoming phits). 6) Flexible design of the NM in software facilitates the addition of features such as security and support of priorities and deadlines for Quality-of-Service (QoS).

2016

— IP-based platforms with Network on Chip (NoC) are one solution to support complex telecommunication applications. In this context, NoC architectures targeting high throughput applications tend to have configurable Network Interfaces (NI) and routers for reuse and performance purposes and aims at providing advanced communication and computation services. Unfortunately, these Network Interfaces are increasingly complex to parameterize and to program, while the deployment tools taking into account the low level architectural details are still non existent. This work focuses on providing methods and tools to easily and efficiently deploy applications on IP and NoC based platform with configurable NI. Configurable NI offer primitives to synchronize and schedule the communication and the behaviour model of the HW platform, of the application and of the mapping, and generates most of the required configurations. The efficiency of the approach is illustrated by the deployment of a complex...

… and Test in Europe-Volume 3, 2005

The MultiNoC system implements a programmable onchip multiprocessing platform built on top of an efficient, low area overhead intra-chip interconnection scheme. The employed interconnection structure is a Network on Chip, or NoC. NoCs are emerging as a viable alternative to increasing demands on interconnection architectures, due to the following characteristics: (i) energy efficiency and reliability; (ii) scalability of bandwidth, when compared to traditional bus architectures; (iii) reusability; (iv) distributed routing decisions. An external host computer feeds MultiNoC with application instructions and data. After this initialization procedure, MultiNoC executes some algorithm. After finishing execution of the algorithm, output data can be read back by the host. Sequential or parallel algorithms conveniently adapted to the MultiNoC structure can be executed. The main motivation to propose this design is to enable the investigation of current trends to increase the number of embedded processors in SoCs, leading to the concept of "sea of processors" systems.

… Logic and Applications, 2003

Abstract. In complex reconfigurable SoCs, the dynamism of applica-tions requires an efficient management of the platform. To allow run-time allocation of resources, operating systems and reconfigurable SoC plat-forms should be developed together. The operating system ...

Networks-on-chip (NoCs) are already a common choice of communication infrastructure for complex systems-on-chip (SoCs) containing a large number of processing resources and with critical communication requirements. A NoC provides several advantages, such as higher scalability, efficient energy management, higher bandwidth and lower average latency, when compared to bus-based systems. Experiments with applications running on NoCs with more than 10% of bandwidth usage show that most of a typical message latency refers to buffered packets waiting to enter the NoC, while the latency portion that depends on packets traversing the NoC is often negligible. This work proposes a Monitored NoC called MoNoC, which is based on a monitoring mechanism and on the exchange of high-priority control packets. Practical experiments show that our fast adaptation method enables transmitting packets with smaller latencies, by using non-congested NoC areas, which reduces the most significant part of message latency.

2002

We propose a packet switched platform for single chip systems which scales well to an arbitrary number of processor like resources. The platform, which we call Network-on-Chip (NOC), includes both the architecture and the design methodology.

2006 International Conference on Field Programmable Logic and Applications, 2006

A modern SoC design comprises dozens of dedicated IP cores for specialized tasks and processors for generalpurpose tasks. Flexibility is the key feature of processors, since it is easy to modify their tasks behavior at runtime. However, most current SoCs have no capability to modify the hardware behavior or structure after system fabrication. On the other hand, to cope with current SoC internal communication complexity, suggestions to employ Networks on Chip (NoCs) are becoming widespread. This paper proposes to extend the inherent software flexibility to hard IP cores in SoCs using NoCs as the main internal communication resource. This is achieved by making IP cores reconfigurable. The paper advances two main contributions: first, a straightforward design flow for SoCs with reconfigurable IP cores; second, the proposition of a NoC, named Artemis, supporting IP core reconfiguration.

IEEE Transactions on Computers, 2000

The adoption of Networks-on-chip (NoCs) as the communication infrastructure for complex integrated systems is a fact, and has been promoted by the growing number of processing elements integrated in current MPSoCs. These are designed to execute several applications in parallel, with different communication requirements and distinct levels of required quality of service. To meet these restrictions, most designs customize the MPSoC at design time, using specific NoC communication services as adaptive routing algorithms, priorities, and connections. However, MPSoCs are increasingly used in embedded systems, where new applications may be added at run-time, characterizing dynamic workload scenarios. Such scenarios require adaptability at runtime, with applications having the possibility to select the most appropriate communication service according to their respective requirements. The goal of the present work is to link the hardware level of NoCs to the MPSoC application level, proposing the development of a communication API that exposes the communication services offered by the NoC to the application developer. Executing real and synthetic applications in two different MPSOCs, and using four different NoC communication services enabled to demonstrate the efficiency of the proposed approach to meet applications requirements.