Dynamic Compaction in SAT-Based ATPG

To cope with the problems of technology scaling, a robust design has become desirable. Self-checking circuits combined with rollback or repair strategies can provide a low cost solution for many applications. However, standard synthesis procedures may violate design constraints or lead to sub-optimal designs. The SAT-based strategies for the verification and synthesis of self-checking circuits presented in this paper can provide efficient solutions.

International Journal of Parallel Programming, 2010

We present the automatic test pattern generator TIGUAN based on a thread-parallel SAT solver. Due to a tight integration of the SAT engine into the ATPG algorithm and a carefully chosen mix of various optimization techniques, multimillion-gate industrial circuits are handled without aborts. TIGUAN supports both conventional single-stuck-at faults and sophisticated conditional multiple stuck-at faults which allows to generate patterns for non-standard fault models.

37th International Symposium on Multiple-Valued Logic (ISMVL'07), 2007

The clock rate of modern chips is still increasing and at the same time the gate size decreases. As a result, already slight variations during the production process may cause a functional failure. Therefore, dynamic fault models like the gate delay fault model are becoming more important. Meanwhile classical algorithms for test pattern generation reach their limits regarding run time and memory needs. In this work, a SAT-based approach to calculate test patterns for gate delay faults is presented. The basic transformation is explained in detail. The application to industrial circuits-where multi-valued logic has to be consideredis studied and experimental results are reported.

2009 17th IFIP International Conference on Very Large Scale Integration (VLSI-SoC), 2009

Due to ever increasing design sizes more efficient tools for Automatic Test Pattern Generation (ATPG) are needed. The application of the Boolean satisfiability problem (SAT) to ATPG has been shown to be a robust alternative to traditional ATPG techniques. A major challenge of research in the field of SAT-based ATPG is to obtain a robust algorithm which can solve hard SAT instances reliably without slowing down easy-to-solve SAT instances. This is particular important, since easy-to-solve SAT instances form the majority of an ATPG run. This paper proposes two structural heuristics. The first one uses testability measurements to obtain an improved initial variable order, while the second heuristic prunes many easy-to-test faults by finding easy-to-control paths. Experimental results on large industrial designs confirm that the proposed methodologies result in a significant overall speed-up.

2009 22nd International Conference on VLSI Design, 2009

We present the automatic test pattern generator TIGUAN based on a thread-parallel SAT solver. Due to a tight integration of the SAT engine into the ATPG algorithm and a carefully chosen mix of various optimization techniques, multimillion-gate industrial circuits are handled without aborts. TIGUAN supports both conventional single-stuck-at faults and sophisticated conditional multiple stuck-at faults which allows to generate patterns for non-standard fault models.

2007

Due to ever increasing design sizes, more ecient tools for Automatic Test Pattern Generation (ATPG) are needed. Recently, SAT-based approaches for test pattern generation have been shown to be very ecient even on large industrial circuits. But these SAT-based techniques are not always superior to classical ATPG approaches. An integration of SAT-based engines into the classical ATPG flow can improve

SAT-based ATPG has proven to be a beneficial complement to traditional ATPG techniques. The generation of a CNF-representation is a vital issue in SAT-based test pattern generation. Firstly, the generation of the problem instances for SAT-based ATPG requires a significant portion of the overall runtime. Secondly, the performance of the SAT solver strongly depends on the properties of the resulting CNF-representation.

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2019

As the complexity of digital designs continuously increases, existing methods to ensure their correctness are facing more serious challenges. Although many studies have been provided to enhance the efficiency of debugging methods, they are still suffering from the lack of scalable automatic correction mechanisms. In this paper, we propose a method for correcting multiple design bugs in gate level circuits. To reduce the correction time, an incremental satisfiability based mechanism is proposed which not only does not require a complete set of test patterns to produce a gate level implementation which does not exhibit erroneous behavior, but also will not reintroduce old bugs after fixing new bugs. The results show that our method can quickly and accurately suggest corrected gates even for large industrial circuits with many bugs. Average improvements in terms of the runtime and memory usage in comparison with existing methods are 2.8× and 6.5×, respectively. Also, the results show that our method compared to the state-of-the-art methods needs 2.6× less test patterns.

Circuits and Systems, 2013

Advancements in semiconductor technology are making gate-level test generation more challenging. This is because a large amount of detailed structural information must be processed in the search process of automatic test pattern generation (ATPG). In addition, ATPG needs to deal with new defects caused by process variation when IC is shrinking. To reduce the computation effort of ATPG, test generation could be started earlier at higher abstraction level, which is in line with top-down design methodology that has become more popular nowadays. In this research, we employ Chen's high-level fault model in the high-level ATPG. Besides shorter ATPG time as shown in many previous works, our study showed that high-level ATPG also contributes to test compaction. This is because most of the high-level faults correlate with the gate-level collapsed faults especially at input/output of the modules in a circuit. The high-level ATPG prototype used in our work is mainly composed by constraint-driven test generation engine and fault simulation engine. Experimental result showed that more reduced/compact test set can be generated from the high-level ATPG.

Increase in transistor density has a great impact on testing as well as design. In worst case, test complexity increases exponentially with number of transistors and number of flipflops. The amount of data and complexity of data generation required to test ICs is growing rapidly in each new generation of technology. The current generation commercially available ATPG and DFT tools are very costly as well as very opaque in terms of their algorithms and implementations. So to demonstrate all the concepts related with testing of combinational VLSI design with an academic perception, this paper talks about building an Automatic Test Pattern Generator tool. This tool uses mostly all the concepts of test set generation for combinational VLSI design like stuck at faults, complete fault list, fault reduction, fault equivalence, fault dominance, testability measures like controllability-observability, line justification, error propagation, reconvergent fan-out, fault coverage, test set compaction, complete test set and so on. It also provides the scope to introduce the need and use of higher level ATPG algorithms. The results are proven using ISCAS benchmark circuits and some other circuits also. The second goal was to avail an open source ATPG tool in its advance form. The ATPG is transparent in nature and demonstrates all the concepts of test pattern generation. As well as it will be ready for open source with some modifications.