A data compression technique for built-in self-test

2014

The design of space-efficient support hardware for built-in self-testing is of great significance in very large scale integration circuits and systems, particularly in view of the paradigm shift in recent times from system-on-board to system-on-chip technology. The subject paper proposes a new approach to designing aliasing-free or zero-aliasing space compaction hardware targeting specifically embedded cores-based system-on-chips for single stuck-line faults extending well-known concept from conventional switching theory, viz. that of compatibility relation as used in the minimization of incomplete sequential machines. For a pair of response outputs of the circuit under test, the method introduces the notion of fault detection compatibility and conditional fault detection compatibility (conditional upon some other response output pair being simultaneously fault detection compatible) with respect to two-input XOR/XNOR logic. The process is illustrated with design details of space compressors for the International Symposium on Circuits and Systems or ISCAS 85 combinational and ISCAS 89 full-scan sequential benchmark circuits using simulation programs ATALANTA and FSIM, attesting to the usefulness of the technique for its relative simplicity, resultant low area overhead and full fault coverage for single stuck-line faults, thus making it suitable in commercial design environments.

IEEE Transactions on Instrumentation and Measurement, 2003

The design of efficient time compression support hardware for built-in self-testing (BIST) is of great importance in the design and manufacture of VLSI circuits. The test data outputs in BIST are ultimately compressed by the time compaction hardware, commonly called a response analyzer, into signatures. Several output response compaction techniques to aid in the synthesis of such support circuits already exist in literature, and parity bit signature coupled with exhaustive testing is already well known to have certain very desirable properties in this context. This paper reports new time compaction techniques utilizing the concept of parity bit signature that facilitates implementing such support circuits using nonexhaustive or compact test sets, with the primary objective of minimizing the storage requirements for the circuit under test (CUT) while maintaining the fault coverage information as best as possible. Recently, Jone and Das proposed a multiple-output parity bit signature generation method extending the basic idea of Akers, for exhaustive testing of digital combinational circuits, where, given a multiple-output circuit, a parity bit signature is generated by first XORing all the outputs to produce a new output function and then feeding this resulting function to a single-output parity bit signature generator. The method, as shown by the authors, preserves all the desirable properties of the conventional single-output response analyzers and can also be easily implemented by using the current VLSI technology. The subject paper further augments the aforesaid concepts of Jone and Das, and proposes a multiple-output parity bit signature for nonexhaustive testing of VLSI circuits. Design algorithms are proposed in the paper, and the simplicity and ease of their implementations are demonstrated with examples. Extensive simulation experiments on ISCAS 85 combinational benchmark circuits using FSIM, ATALANTA, and COMPACTEST programs demonstrate that the proposed signature generation method achieves high fault coverage for single stuck-line faults, with low CPU simulation time, and acceptable area overhead. A performance comparison of the designed time compactors with conventional space-time compaction is also presented to demonstrate improved tradeoff for the new circuits in terms of fault coverage and the CUT resources consumed contrasted with existing designs, and to appreciate the resulting performance enhancements.

Proceedings of the 22nd Annual Symposium on Integrated Circuits and System Design: Chip on the Dunes, 2009

The claim for new functionalities regarding the improvement of dependability of electronic systems and also the need for managing the time spent during test make the Built-in-Self-Test mechanism (BIST) a promising feature to be integrated in current IC flows. There are a lot of types of BIST: Memories BIST, Logical BIST (LBIST) and also some mechanisms used to test analog parts of circuit. Traditional LBIST uses on-chip hardware to generate all test patterns with a pseudo-randompattern-generator (PRPG) and analyze the output signature generated by a multiple-input-signature-register (MISR). This approach requires the insertion of extra test-points or storing information outside chip to enable achieving a test coverage >98%. Also generating all test stimuli implies in a sacrifice of test application time, which can be acceptable for some small systems to perform self-test during boot up but could become a negative aspect when testing System-on-chip (SOC) ICs. The current IC development flow insert scan chains and generates automatically scan tests patterns to achieve high fault coverage for manufacturing test. Scan data compression techniques have proven to be very useful for reducing test cost while reducing test data volume and test application time. This work proposes the reuse of compressed scan test patterns used during manufacturing test to implement a LBIST with the goal of testing the circuit when it is already in field. The proposed LBIST mechanism aims to uncover defects that could occur due to the wear out of the circuit. A scan test pattern based LBIST architecture and a semi-automatic development flow are proposed and validated in a real word SoC testcase.

We propose a method for reducing test data volume of integrated circuits or cores in a System-on-Chip. This method is intended to reduce the required number of Automatic Test Equipment (ATE) output channels compared to the number of scan-in input pins in a classical multi-chain implementation (horizontal compression). Compression and decompression are based on arithmetic operations and structures which present a very low area overhead. The proposed compression scheme does not impact the fault coverage achieved by the original test sequence before compression.

Proceedings Twelfth International Conference on VLSI Design. (Cat. No.PR00013), 1999

Generalized Modified Positional Syndrome (GMPS), of order p, a new compaction scheme for test output data is presented. The order p determines the alising probability and the amount of hardware overhead required to implement the scheme. GMPS of order two gives an aliasing probability about an order of magnitude lower than the best scheme reported in literature with minimal extra hardware. A hardware realization scheme for GMPS has been presented. The scheme uses adders with feedback.

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2003

Test sets for path delay faults in circuits with large numbers of paths are typically generated for path delay faults associated with the longest circuit paths. We show that such test sets may not detect faults associated with the next-to-longest paths. This may lead to undetected failures since shorter paths may fail without any of the longest paths failing. In addition, paths that appear to be shorter may actually be longer than the longest paths if the procedure used for estimating path length is inaccurate. We propose a test enrichment procedure that increases significantly the number of faults associated with the next-to-longest paths that are detected by a (compact) test set. This is achieved by allowing the underlying test generation procedure the flexibility of detecting or not detecting the faults associated with the next-to-longest paths. Faults associated with next-to-longest paths are detected without increasing the number of tests beyond that required to detect the faults associated with the longest paths. The proposed procedure thus improves the quality of the test set without increasing its size.

Proceedings of the Ninth Asian Test Symposium, 2000

We present a new test generation procedure for sequential circuits using newly traversed state and newly defectedfault inforination obtained between successive iterations of vector compaction. Two types of techniques are considered. One is based on which new states a sequential circuit is driven into, and the other is based on the new faults that are detected in the circuit between consecutive iterations of vector compaction. These dcita niodifi an otherwise random selection of vectors, to bias vector sequences that cause the circuit to reach new states, and cause previously undetected faults to be detected. The biased vectors, when used to extend the conipacted test set, provide an intelligent selection of vectors. The extended test set is then conipacted. Repeated npplications of state and fault analysis, vector generation and compaction produce signifcantLy high fault coverage using relatively sniall computing resources. We obtained improvements in terms of higher fault coverage, fewer vectors for the same coverage, or smaller nuniber of iterations arid time required, consistently for several benchniark circuits.

IET Computers & Digital Techniques, 2008

Test data compression is an effective methodology for reducing test data volume and testing time. In this paper, we present a new test data compression technique based on block merging. The technique capitalizes on the fact that many consecutive blocks of the test data can be merged together. Compression is achieved by storing the merged block and the number of blocks merged. It also takes advantage of cases where the merged block can be filled by all 0's or all 1's. Test data decompression is performed on chip using a simple circuitry that repeats the merged block the required number of times. The decompression circuitry has the advantage of being test data independent. Experimental results on benchmark circuits demonstrate the effectiveness of the proposed technique compared to other coding-based compression techniques.

In this paper, we propose a new programmable deterministic Built-In Self-Test (BIST) method that requires significantly lower storage for deterministic patterns than existing programmable methods and provides high flexibility for test engineering in both internal and external test.

Microelectronics Reliability, 2018

This paper describes a test response compaction method that preserves diagnostic information and enables performing a test-per-clock offline test. The test response compaction system is based on a chain of T flip-flops. The T flip-flop signature chain can preserve the information about the positions of the erroneous test response occurrence and the information about the clock cycle when the erroneous test responses occurred. This information can be used for diagnostic purposes. An algorithm that localizes errors according to the T flip-flop chain output is presented. The paper discusses the possible benefits and limitations of the proposed test pattern compaction scheme. The influence of multiple errors on detection and localization capability of the compaction system and hardware overhead is discussed in the paper as well. The probability of error masking is analyzed, the proposed scheme provides substantially lower masking probability than a D flip-flop chain and a MISR. The scheme can spare the test time by the test-per-clock arrangement. The hardware overhead and reached test time are given for several benchmark circuits in the paper as well.