Test data compression based on input-output dependence

2004

Test sets for path delay faults in circuits with large numbers of paths are typically generated for faults associated with the longest circuit paths. Such test sets may not detect faults associated with the next-to-longest paths. This may lead to undetected failures. A dynamic test enrichment procedure proposed earlier increases the number of faults associated with the next-to-longest paths that are detected by a test set in order to improve its quality without increasing its size. The earlier procedure is referred to as dynamic since the decision as to which faults associated with next-to-longest paths will be detected is done during test generation. In this work, we describe a postprocessing procedure for test enrichment that accepts a given test set. By processing the tests in reverse order, the proposed procedure increases the number of detected faults associated with next-to-longest paths without increasing the number of tests. We demonstrate the effectiveness of the proposed reverse order test enrichment procedure when applied following, and instead of, dynamic test enrichment.

1991, Proceedings. International Test Conference, 1991

The path delay fault model is arguably the strongest model for real delay defects in circuits. The recent availability of fully path delay f u l t testable designs has made it feasible to consider the problem of making test application for path delay faults more efficient by reducing the sizes of the potentially large test-sets required to obtain satisfactory coverages. This paper presents, for the first time, a heuristic-driven test generation procedure for obtaining maximal multiple-path-propagating robust tests, which detect the largest possible number of path faults simultaneously. Extensive experimental results are presented to demonstrate the efficacy of this approach, which is seen to significantly reduce test-set lengths for path delay faults by generating highly efficient robust tests.

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1998

We present a method for test-point insertion in large combinational circuits, to increase their path delay fault testability. Using an appropriate test application scheme with multiple clock periods, a test point on a line g divides the set of paths through g for testing purposes into a subset of paths from the primary inputs up to g; and a subset of paths from g to the primary outputs. Each one of these subsets can be tested separately. The number of paths that need to be tested directly is thus reduced. In addition, by breaking an untestable path into two or more testable subpaths, it is possible to obtain a fully testable circuit. Test-point insertion is done to reduce the number of paths, using a time-efficient procedure. Indirectly, it also reduces the number of tests and renders untestable paths testable. When the number of paths is sufficiently small, and if the test generation procedure to be used for the circuit is known, a procedure is given to perform test-point insertion directly targeting the path delay faults that are still untestable. Experimental results are presented to demonstrate the effectiveness of the proposed methods in increasing the testability of large benchmark circuits, and to demonstrate the overheads involved.

Proceedings of 9th International Conference on VLSI Design, 1995

W e propose a coverage metric and a two-pass test generation method f o r path delay faults in combinational logic circuits. The coverage is measured f o r each line with a rising and a falling transition. However, the test criterion is different from that of the slow-to-rise and slow-to-fall transition faults. The test, called "line delay test", as a path delay test for the longest sensitizable path producing a given transition on the target line. The maximum number of tests (and faults) is limited to twice the number of lines. However, the line delay test criterion resembles path delay test and not the gate or transition delay test. Using a two-pass test generation procedure, we begin with a minimal set of longest paths covering all lines and generate tests for them. Fault simulation is used to determine the coverage metric. For uncovered lines, an the second pass, several paths of decreasing length are targeted. W e present a theorem stating that a redundant stuck-at fault makes all path delay faults involving the faulty line untestable for either a rising or falling transition depending on the type of the stuck-at fault. The use of this theorem considerably reduces the effort of delay test generation. W e give results on benchmark circuits.

VLSI Design, 1995., …, 1995

The new test pattern generation system for path delay faults in combinational logic circuits considers robust and nonrobust tests, simultaneously. Once a robust test is obtained for a path with a given transition, another test for the same path with the opposite transition ...

1995

In this paper, we classify path-delay faults into three categories: singly-testable (ST), multiply-testable (MT), and singly-testable dependent (ST-dependent). All ST faults are guaranteed detection in the case of a single fault, and some may be guaranteed detection through robust and validatable non-robust tests even in the case of multiple faults. An ST-dependent fault can affect the circuit speed only if certain ST faults are present. Thus, if the ST faults are tested, the ST-dependent faults need not be tested. MT faults cannot be guaranteed detection, but affect the speed only if delay faults simultaneously exist on a set of paths none of which is ST. We classify all path-delay faults into the three categories by a procedure using any unaltered single stuck fault test generation tool. We use only two runs of this tool on a network derived from the original network. As a by-product of this process, we generate single and multiple input change delay tests for all testable faults. With these tests, we expect that most defective circuits are identified. Examples and results on ISCAS'89 benchmarks are presented

Journal of Electronic Testing, 1997

We classify all path-delay faults of a combinational circuit intothree categories: singly-testable (ST), multiply-testable (MT), and singly-testable dependent} (ST-dependent). The classification uses anyunaltered single stuck-at fault test generation tool. Only two runsof this tool on a model network derived from the original network areperformed. As a by-product of this process, we generate single andmultiple input change delay tests for all testable faults. With thesetests, we expect that most defective circuits are identified. All STfaults are guaranteed detection in the case of a single fault, andsome may be guaranteed detection through robust and validatablenon-robust tests even in the case of multiple faults. An ST-dependentfault can affect the circuit speed only if certain ST faults arepresent. Thus, if all ST faults are tested, the ST-dependent faultsneed not be tested. MT faults cannot be guaranteed detection, butaffect the speed only if delay faults simultaneously exist on a setof paths, none of which is ST. Examples and results on several ISCAS‘89 benchmarks are presented. The method of classification throughtest generation using a model network is complex and can be appliedto circuits of moderate size. For larger circuits, alternativemethods will have to be explored in the future.

1992

Abstruct-A method to estimate the coverage of path delay faults of a given test set, without enumerating paths, is proposed. The method is polynomial in the number of lines in the circuit, and thus allows circuits with large numbers of paths to be considered under the path delay fault model. Several levels of approximation, with increasing accuracy and increasing polynomial complexity, are proposed. Experimental results are presented to show the effectiveness and accuracy of the estimate in evaluating the path delay fault coverage. Combining this non-enumerative estimation method with a test generation method for path delay faults would yield a cost effective method to consider path delay faults in large circuits, which are beyond the capabilities of existing test generation and fault simulation procedures, that are based on enumeration of paths.

2003

Reducing test data size is one of the major challenges in testing systems-on-a-chip. This can be achieved by test compaction and/or compression techniques. Having a partially specified or relaxed test set increases the effectiveness of compaction and compression techniques. In this paper, we propose a novel and efficient test relaxation technique for combinational circuits. It is based on critical path tracing and hence it may result in a reduction in the fault coverage. However, based on experimental results on ISCAS benchmark circuits, the drop in the fault coverage (if any) after relaxation is small for most of the circuits. The technique is faster than the brute-force test relaxation method by several orders of magnitude.

2003

Two-pattern test is required to identify delay faults in a circuit. The importance of delay fault testing is increasing gradually because of the fact that traditional stuck-at fault testing is failing to guarantee an acceptable quality level for today's high-speed chips. Some defects and/or random process variation do not change the steady state behavior of a circuit but affect the at speed performance. Any degradation in at speed performance is detected by delay testing and it is likely to become industrially accepted in near future. A straightforward solution to two-pattern testability is the enhanced-scan design. But this incorporates very high area overhead and long test application time. In this thesis we present a hierarchical testability technique for delay faults. There are a number of delay fault models. Among these, the path delay fault model is more general and can overcome the limitations of other models. Our approach is developed on path delay fault model. The design hierarchy we consider is (Register Transfer Level) RTL, where the number of primitive elements in the circuit is greatly reduced. At RTL a circuit can be divided into two parts: a controller and a data path. Firstly, we consider the data path as a separate entity. We introduce the concept of RTL paths in a data path. Based on this we develop the definition of hierarchically twopattern testable (HTPT) data path. The advantages of an HTPT data path are (i) the data path can be tested using any delay fault model, (ii) combinational (Automatic Test Pattern Generation) ATPG can be used and (iii) the same fault coverage can be obtained as with the enhanced scan approach. We also point out some necessary and sufficient conditions to support the propagation of two-pattern vectors via two or more control paths in a data path.