Multilevel logic synthesis for arithmetic functions

1995

There are many methods for the synthesis of logical functions. All these methods can be divided into two classes the first one is Two-Level Logic Synthesis and the second one is Multi-Level Logic Synthesis. The multi-level circuits and their structure are easier for practical realization if there is a large number of variables. In this paper we concentrate on a part of the second class - synthesis of multi-level-circuits with EXOR-gates. We present six methods for EXOR-decomposition for both, completely and incompletely specified functions. In detail, we give an iterative algorithm for checking and calculating the EXOR - groupability for the incompletely specified functions relating to sets of variables. Using this method, it is possible to fully utilize the characteristics and properties of incompletely specified functions enabling synthesis of very efficent circuits.

VLSI Design, 1995

During the last decade, many different approaches have been proposed to solve the multiple-level synthesis problem with different minimum functionally complete systems of primitive logic blocks. The most popular of them is the division-based approach. However, modem microelectronic technology provides a large variety of building blocks which considerably differ from those typically considered. The traditional methods are therefore not suitable for synthesis with many modem building blocks. Furthermore, they often fail to find global optima for complex designs and leave unconsidered some important design aspects. Some of their weaknesses can be eliminated without leaving the paradigm they are based on, other ones are more fundamental. A paradigm which enables efficient exploitation of the opportunities created by the microelectronic technology is the general decomposition paradigm. The aim of this paper is to analyze and compare the general decomposition approach and the division-based approach. The most important advantages of the general decomposition approach are its generality (any network of any building blocks can be considered) and totality (all important design aspects can be considered) as well as handling the incompletely specified functions in a natural way. In many cases, the general decomposition approach gives much better results than the traditional approaches.

VLSI Design, 1999

A new method for implementing two-level logic circuits, which exhibit minimal power dissipation, is introduced. Switching activity reduction of the logic network nodes is achieved by adding extra input signals to specific gates. Employing the statistic properties of the primary inputs, a new concept for grouping the input variables with similar features is introduced. Appropriate input variables are chosen for reducing the switching activity of a logic circuit. For that purpose, an efficient synthesis algorithm, which generates the set of all groups of the variables and solves the minimum covering problem for each group is developed. The comparison of the results, produced by the proposed method, and those from ESPRESSO shows that a substantial power reduction can be achieved.

VLSI Design, 1995

This paper introduces several new families of decision diagrams for multi-output Boolean functions. The introduced families include several diagrams known from literature (BDDs, FDDs) as subsets. Due to this property, these diagrams can provide a more compact representation of functions than either of the two decision diagrams. Kronecker Decision Diagrams (KDDs) with negated edges are based on three orthogonal expansions (Shannon, Positive Davio, Negative Davio) and are created here for incompletely specified Boolean functions as well. An improved efficient algorithm for the construction of KDD is presented and applied in a mapping program to ATMEL 6000 fine-grain FPGAs. Four other new families of functional decision diagrams are also presented: Pseudo KDDs, Free KDDs, Boolean Ternary DDs, and Boolean Kronecker Ternary DDs. The last two families introduce nodes with three edges and require AND, OR and EXOR gates for circuit realization. There are two variants of each of the last two...

Journal of King Abdulaziz University-Engineering Sciences, 2006

This note proposes a minor modification of a recently-developed method that achieves two-level multipleoutput logic minimization via the constrained minimization of a single function. The modified method is simpler and more efficient than the original one, but unlike the original method, it does not guarantee exact minimality except for small-size circuits.

In this paper, we consider the problem of logic simplification for a special class of logic functions, namely complementary Boolean functions (CBF), targeting low power implementation using static CMOS logic style. The functions are uniquely characterized by the presence of terms, where for a canonical binary 2-tuple, D(m j ) ∪ D(m k ) = { } and therefore, we have | D(m j ) ∪ D(m k ) | = 0 [19]. Similarly, D(M j ) ∪ D(M k ) = { } and hence | D(M j ) ∪ D(M k ) | = 0. Here, 'm k ' and 'M k ' represent a minterm and maxterm respectively. We compare the circuits minimized with our proposed method with those corresponding to factored Reed-Muller (f-RM) form, factored Pseudo Kronecker Reed-Muller (f-PKRM) form, and factored Generalized Reed-Muller (f-GRM) form.

To achieve the reduction of power consumption, optimizations are required at various levels of the design steps such as algorithm, architecture, logic and circuit & process techniques. This paper considers the two logic level approaches for low power digital design. Optimization techniques are carried to reduce switching activity power of individual logic-gates. we can reduce the power by using either circuit level optimization or logical level optimization. In this paper, the circuit level optimization process is followed to reduce the area and power. In the first approach, Modified gate diffusion input (GDI) logic is used in the proposed parallel asynchronous self time adder (PASTA) technique. Similarly, the structure of XOR gate and half adder is reduced to achieve the low area and low power. In second approach, Multi value logic based digital circuit is designed by increasing the representation domain from the two level (N=2) switching algebra to N > 2 levels. The main advantage of this approach is to compensate the inefficiency of existing integrated circuits that are used to implement the universal set of MVL gates. From the results, the proposed GDL logic based Adder offers less number of transistors (area) and low power consumption than the existing technique. And proposed MVL technique allows designing MVL digital circuit that is set to obtain the values from the binary circuits. Also this technique offers low power and small wiring delay, when compared to binary and three value logic. The simulation process is carried out by tanner toolv14.11 to check the functionality of the PASTA & MVL circuits. A. Proposed Modified Gdi Logic In day today life, the Systems on Chip (SoC) product are necessary. Millions of chip integrated into one single chip is called as SoC. These millions of chip are integrated into single chip by shrinking the transistor size in each and every chip. Therefore this CMOS technique can apply in SoC product [3]. Carry Select Adder (CSLA) is primarily used to minimize the chip size and for reducing the propagation delay. The parallel asynchronous self time adder (PASTA) is working based on iterative coding. So the number of unwanted activation of clock cycle is removed in this adder to achieve the high speed and low power. This type of adder will be designed in this paper in two ways [10]. The Gate Diffusion Input (GDI) technique is proposed in 2002 to reduce the area and power of VLSI digital circuits. The GDI logic was initially proposed for fabrication in twin-well and Silicon on Insulator (SOI) CMOS methods. It enabled the implementation of a broad range of difficult logic functions using simply two transistors. This scheme was appropriate for the design of regular digital circuits, with a much lower area than existing PTL and Static CMOS methods, whereas offering improved power characteristics. Equally to PTL implementations, the GDI circuits suffered from a decreased swing because of threshold drops. Conversely, a considerably shrinked the logic flexibility and transistor count of the basic GDI cell, gives major power reduction, in spite of the need for swing restoration circuits [1]. B. Proposed MVL Logic The MVL is also known as multiple-valued, multi-valued or many-valued logic that traces its origins back to the Lukasiewicz logic and Post algebra. The proposed methodology in this work is based on a universal set of gates that is used to implement operators acting on the elements of a domain. The current trend in Integrated Circuits (IC) is to embed multiple systems onto a single IC, known as System on a Chip (SoCs) leading to, factors like, an increment in the quantity, the delay time, length, and complexity of the interconnections. The multiple-valued logic is a viable alternative to cope up with the issues due to interconnections, as they are said to decrease the number of the interconnections. This reduction in the area of the IC devoted to the interconnections has motivated many MVL proposals. Methodologies for the synthesis of MVL digital circuits comprise of the operators and their properties. Main drawbacks of such methodologies are: first, the lack of existing integrated circuits that implement the universal set of gates and, second minimization tools needed to design practical MVL digital circuits.

IEE Proceedings - Computers and Digital Techniques, 1996

An algorithm called XOF.GA is presented which minimises Boolean mult i-output logic functions as multilevel ANDEXOR networks of two-input logic gates. It carries out symbolic simplification, and works from tlhe bottom of a binary variable decision tree to tlhe top, with variable choice determined using a genetic algorithm. Since the algorithm is multilevel in nature, it delivers more compact circuits than two-level ESOP minimisation algorithrrts, such as EXMIN2. it also finds more economical representations than the fixed polarity Ree& Muller method.

Radio and Electronic Engineer, 1969

A pencil-and-paper method of designing multi-level logic circuits is presented. The approach is intuitive rather than systematic. It bears the same relation to the design of circuits with gates of limited fan-in (as is the case with most microcircuit families) as does the Karnaugh-map method to two-level circuits and gates with unlimited fan-in, NAND/NOR systems are considered, and a graphical procedure, based on Karnaughmaps, is followed.