Efficient DSP implementation of an LDPC decoder
Markus Rupp2004, Acoustics, Speech, and Signal …
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Abstract
We present a high performance implementation of a belief propagation decoder for decoding low-density parity-check (LDPC) codes on a fixed point digital sig-nal processor. A simplified decoding algorithm was used and a stopping criteria for the iterative decoder was ...
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Low density parity check (LDPC) codes over GF(2m) are an extension of binary LDPC codes with significantly higher performance. However, the computational complexity of the encoders/decoders for these codes is also higher. Hence there is a substantial lack of hardware implementations for LDPC over GF(2m) codes. This paper proposes a novel variation of the belief propagation algorithm for GF(2m) LDPC codes. The new algorithm results in a reduced hardware complexity when implemented in VLSI. The serial architecture of the novel decoding algorithm and two other algorithms for LDPC over GF(2m) are implemented on an FPGA. The results show that the proposed algorithm has substantial advantages over existing methods. We show that the implementation of LDPC over GF(2m) decoder is feasible for short to medium length codes. The additional complexity of the decoder is balanced by the superior performance of GF(2m) LDPC codes.
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In this paper, we proposed a Parallel-Layered Belief-Propagation (PLBP) algorithm first, which makes a breakthrough in utilizing the layered decoding algorithm on the "non-layered" quasi-cyclic (QC) LDPC codes, whose column weights are higher than one within layers. Our proposed PLBP algorithm not only achieves a better error performance, but also requires almost 50% less iterations, compared with the original flooding algorithm. Then we propose a low-power partial parallel decoder architecture based on the PLBP algorithm. The PLBP decoder architecture requires less area and energy efficiency than other existing decoders. As a case study, a multi-rate 9216-bit LDPC decoder is implemented in SMIC 0.13 m 1P6M CMOS technology. The decoder dissipates an average power of 87mW with 10 iterations at a clock frequency of 83.3 MHz. The chip core size is 7.59 mm 2 , and the die area occupies 10.82 mm 2 .
Transactions Papers Reduced-Complexity Decoding of LDPC Codes
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In this paper, two simplified versions of the belief propagation algorithm for fast iterative decoding of low-density parity check codes on the additive white Gaussian noise channel are proposed. Both versions are implemented with real additions only, which greatly simplifies the decoding complexity of belief propagation in which products of probabilities have to be computed. Also, these two algorithms do not require any knowledge about the channel characteristics. Both algorithms yield a good performance-complexity tradeoff and can be efficiently implemented in software as well as in hardware, with possibly quantized received values.
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This paper introduces a new approach to costeffective, high-throughput hardware designs for Low Density Parity Check (LDPC) decoders. The proposed approach, called Non-Surjective Finite Alphabet Iterative Decoders (NS-FAIDs), exploits the robustness of message-passing LDPC decoders to inaccuracies in the calculation of exchanged messages, and it is shown to provide a unified framework for several designs previously proposed in the literature. NS-FAIDs are optimized by density evolution for regular and irregular LDPC codes, and are shown to provide different trade-offs between hardware complexity and decoding performance. Two hardware architectures targeting high-throughput applications are also proposed, integrating both Min-Sum (MS) and NS-FAID decoding kernels. ASIC post synthesis implementation results on 65nm CMOS technology show that NS-FAIDs yield significant improvements in the throughput to area ratio, by up to 58.75% with respect to the MS decoder, with even better or only slightly degraded error correction performance.
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Low-density parity-check (LDPC) codes are among the most powerful known error correcting codes and they have been shown to achieve performance very close to the Shannon bound. In practical hardware implementations of LDPC decoders, bit error rate performances are affected strongly by fixed-point representation of processed data and, although many papers have been published in recent years on the subject of LDPC codes, only a few of them report results on the effects of finite precision. In the paper two novel arithmetic approximations for the basic processing operations of the decoding algorithm are presented. The two proposed solutions are analysed in terms of bit error rate performance for different finite precison representations of both external and internal data; the estimated performance loss is comparable to that reported by previous works and limited to approximately 0.1 dB for cases of interests. However the proposed solutions support a reduced complexity formulation of the decoding algorithm, so enabling the implementation of flexible decoders that can be adapted to different LDPC codes, block sizes and code rates.
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IEEE Transactions on Communications, 2002
In this paper, we propose a belief-propagation (BP)-based decoding algorithm which utilizes normalization to improve the accuracy of the soft values delivered by a previously proposed simplified BP-based algorithm. The normalization factors can be obtained not only by simulation, but also, importantly, theoretically. This new BP-based algorithm is much simpler to implement than BP decoding as it requires only additions of the normalized received values and is universal, i.e., the decoding is independent of the channel characteristics. Some simulation results are given, which show this new decoding approach can achieve an error performance very close to that of BP on the additive white Gaussian noise channel, especially for low-density parity check (LDPC) codes whose check sums have large weights. The principle of normalization can also be used to improve the performance of the Max-Log-MAP algorithm in turbo decoding, and some coding gain can be achieved if the code length is long enough.
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IEEE Transactions on Communications, 2000
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Various log-likelihood-ratio-based belief-propagation (LLR-BP) decoding algorithms and their reducedcomplexity derivatives for LDPC codes are presented. Numerically accurate representations of the check-node update computation used in LLR-BP decoding are described. Furthermore, approximate representations of the decoding computations are shown to achieve a reduction in complexity by simplifying the check-node update or symbol-node update or both. In particular, two main approaches for simplified check-node updates are presented that are based on the so-called min-sum approximation coupled with either a normalization term or an additive offset term. Density evolution (DE) is used to analyze the performance of these decoding algorithms, to determine the optimum values of the key parameters, and to evaluate finite quantization effects. Simulation results show that these reduced-complexity decoding algorithms for LDPC codes achieve a performance very close to that of the BP algorithm. The unified treatment of decoding techniques for LDPC codes presented here provides flexibility in selecting the appropriate scheme from a performance, latency, computational-complexity and memory-requirement perspective.
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This paper presents a practical method of potential replacement of several different Quasi-Cyclic Low-Density Parity-Check (QC-LDPC) codes with one, with the intention of saving as much memory as required to implement the LDPC encoder and decoder in a memory-constrained System on a Chip (SoC). The presented method requires only a very small modification of the existing encoder and decoder, making it suitable for utilization in a Software Defined Radio (SDR) platform. Besides the analysis of the effects of necessary variable-node value fixation during the Belief Propagation (BP) decoding algorithm, practical standard-defined code parameters are scrutinized in order to evaluate the feasibility of the proposed LDPC setup simplification. Finally, the error performance of the modified system structure is evaluated and compared with the original system structure by means of simulation.
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2007 IEEE International Conference on Signal Processing and Communications, 2007
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Reduced-complexity belief propagation decoding for low-density parity-check codes
Electronics Letters, 2008
A novel dual-min-sum decoding algorithm for low-density paritycheck codes is proposed. The proposed algorithm simplifies the check-node updates and thus reduces the computational complexity of the belief propagation (BP) algorithm significantly. Simulation results show that the proposed algorithm can achieve an error performance very close to that of the BP algorithm.
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IEEE Transactions on Communications, 2000
In this paper, we propose a binary message-passing algorithm for decoding low-density parity-check (LDPC) codes. The algorithm substantially improves the performance of purely hard-decision iterative algorithms with a small increase in the memory requirements and the computational complexity. We associate a reliability value to each nonzero element of the code's parity-check matrix, and differentially modify this value in each iteration based on the sum of the extrinsic binary messages from the check nodes. For the tested random and finitegeometry LDPC codes, the proposed algorithm can perform as close as about 1 dB and 0.5 dB to belief propagation (BP) at the error rates of interest, respectively. This is while, unlike BP, the algorithm does not require the estimation of channel signal to noise ratio. Low memory and computational requirements and binary message-passing make the proposed algorithm attractive for high-speed low-power applications.
Threshold Optimization for Reduced Complexity LDPC Decoding
2007
Low-Density Parity-check codes deliver very good performance when decoded with belief propagation also known as sum product algorithm. Most of the complexity in the belief propagation algorithm rests in the check node processor. This paper presents an overview of the approaches used for reducing the number of active nodes that participate in the decoding iteration loop. Also a novel approach for deciding the initial threshold for optimal elimination of high confidence level is proposed. Merits of the proposed algorithm termed as variable offset constant slope algorithm is discussed.
Improved BP-Based Decoding Algorithms Integrated with GA for LDPC Codes
Advances in Intelligent and Soft Computing, 2009
We proposed two improved decoding algorithms for Low-Density Parity-Check (LDPC) codes based on the Belief-Propagation (BP) algorithm combined with Genetic Algorithm (GA). After giving a genetic interpretation of Tanner graph, GA is adopted to efficiently use the information passing from the variable nodes to the check nodes. Simulation results assert the superiority of our proposed algorithms over the BP algorithm both in BER (Bit Error Rate) and FER (Frame Error Rate). At last, optimization of the key parameter of the developed algorithms is given.
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