A Genetic Algorithm For Vlsi Physical Design Automation

Abstract— The efficient designing of any complex system necessitates decomposition of the same into a set of smaller subsystems and each subsystem can be designed independently to speed up the design process. Partitioning is one of the fundamental problems of VLSI physical design. The aim of present study is to do the Bi partitioning of the VLSI circuit using Hybrid Algorithm. The combination of Simulated annealing and Genetic Algorithm is used to improve the speed while using moderate storage Hybrid Algorithm (HA) is expected to provide better solution with less CPU time. Based on the results of study, the hybrid algorithm is shown to produce promising results when applied to circuit partitioning problem. The algorithm not only balances the size of two portions but also evenly distributes the connections among them. Parent selection strategy employed avoids the premature convergence of HA to a local optimum.

Floorplanning is one of the important issues in the process of very large-scale integrated (VLSI) circuit design. It is generally used to determine the performance and size of VLSI chips. In this paper a novel genetic algorithm is proposed to obtain a feasible floorplanning in VLSI physical circuit design process. Integer coding representation based on module number is used along with the genetic algorithm for optimal placement solution. Various experiments employing GSRC benchmarks demonstrate that the algorithm proposed in this paper is competitive and comparable to other state of the art algorithms. The proposed algorithm can avoid the problem of local minima and performs very well in terms of convergence.

IJCA Proceedings on National …, 2012

Circuit partitioning problem is a well known NP hard problem. The potential of Genetic Algorithm has been used to solve many computationally intensive problems (NP hard problems) because existing conventional methods are unable to perform the required breakthrough in terms of complexity, time and cost. The presented work deals with the problem of partitioning of a circuit using Genetic Algorithm. The program inputs the adjacency matrix, generates graph of the circuit and partitions the circuit based on crossover operator. The program produces a set of vertices that are highly connected to each other but highly disconnected from the other partitions.

South African Computer Journal, 2015

This paper propose a Virtual-Field Programmable Gate Array (V-FPGA) architecture that allows direct access to its configuration bits to facilitate hardware evolution, thereby allowing any combinational or sequential digital circuit to be realized. By using the V-FPGA, this paper investigates two possible ways of making evolutionary hardware systems more scalable: by optimizing the system’s genetic algorithm (GA); and by decomposing the solution circuit into smaller, evolvable sub-circuits. GA optimization is done by: omitting a canonical GA’s crossover operator (i.e. by using a 1+λ algorithm); applying evolution constraints; and optimizing the fitness function. A noteworthy contribution this research has made is the in-depth analysis of the phenotypes’ CPs. Through analyzing the CPs, it has been shown that a great amount of insight can be gained into a phenotype’s fitness. We found that as the number of columns in the Cartesian Genetic Programming array increases, so the likelihood ...

IEEE Transactions on Automatic Control, 1983

In this paper, we present a new methodology for custom VLSI layout which aims at a low turnaround time and a high quality of design. VLSI circuits are highly complex, and to speed up the design process we exploit the hierarchical structure of a design, splitting the problem domain into several levels. The process of layout at each level is divided into steps such as placement of rectangular blocks, determining block dimensions, determining interconnection paths, etc. In order to obtain high quality designs, we have systematically analyzed the relationship among the parameters being computed at various steps and have accordingly organized the flow of data and control through these steps. There are two novel features in our scheme. First, we do not follow the usual pure top-down or pure bottom-up approach, so as to take into account the infl.uence of design decisions at the higher levels on design decisions made at the lower levels, as well as vice versa. For example, we determine the geomehy of a block taking into consideration the context in which it is placed, as well as the geometries of the lower level blocks it encloses. Second, we perform a look-ahead operation when the values of some. parameters are needed before they are actually deterministically computable by the process. For example, at the ,time of placement, the area required for routing is estimated statistically (before doing the actual routing) so that a more routable placement can be obtained, thereby avoiding some unnecessary iterations.

2005

This paper browses through some well-known meta-heuristic search strategies, and briefly discusses some of their recent applications to the VLSI layout design process. It starts with very brief description of the different phases of VLSI layout design, and a brief overview of Meta-Heuristic search strategies. Since most of the VLSI layout design problems are hard optimization problems, the concept of NP-hardness for such problems is next explained along with the various algorithmic frameworks to solve them. Four selected well-known meta-heuristic strategies, namely, Simulated Annealing, Genetic Algorithm, Tabu Search and Ant Colony Optimization are next explained, followed a comparison of these methods. Next, selected applications of these meta-heuristics to VLSI layout design are discussed. Some of their advanced variants and different hybridization techniques, adopted for superior result, are also discussed to highlight the recent research trends in meta-heuristics.

IEEE Transactions on Evolutionary Computation, 2002

We present a genetic algorithm (GA) that uses a slicing tree construction process for the placement and area optimization of soft modules in very large scale integration floorplan design. We have overcome the serious representational problems usually associated with encoding slicing floorplans into GAs, and have obtained excellent (often optimal) results for module sets with up to 100 rectangles. The slicing tree construction process used by our GA to generate the floorplans has a run-time scaling of O(n lg n). This compares very favourably with other recent approaches based on non-slicing floorplans that require much longer run times. We demonstrate that our GA outperforms a simulated annealing implementation with the same representation and mutation operators as the GA.

2014

This paper investigates optimisation of Evolutionary Hardware Systems (EHW) by means of digital circuit critical path analysis. A 2×2 digital multiplier and a Finite State Machine (FSM) control circuit were evolved using a target-independent Virtual Reconfigurable Circuit (VRC) architecture. An in-depth analysis of the phenotypes ’ Critical Paths (CP) was performed. Through analysing the CPs, it was shown that a great amount of insight can be gained into a phenotype’s fitness. Particularly, the identification of the CP’s dependence is valuable, since dependent CPs reduced the required net number of evolved Logic Elements (LE). Generally, in both the multiplier and state phenotypes, the CPs were evolved in ascending order of the net LEs. This suggests that evolution always favoured CPs with lower net numbers. However, we have seen that in one special case, if two independent CPs are used by a third CP, the resulting third CP has a lower net number than both independent CPs. The CP an...

Eleventh Annual International Phoenix Conference on Computers and Communication [1992 Conference Proceedings], 1992

Interconnection and packaging are among the dominant factors that limit the performance of future integrated circuits containing millions of transistors. As chips become more complex, so does the packaging. Design automation is thus without doubt necessary. In this paper, a window based simulation environment called PDSE (Packaging Design Support Environment) which integrates several tools for VLSI interconnection modeling and simulations is presented. We will describe the concept of the automated packaging design cycle, the structure and the components of the simulation environment, and the implementation of an interconnect layout geometry data extractor. Finally a case study will be given to illustrate the entire design process.

Computer Sciences Forum (Honeywell), 1984

This article describes a chip planning tool called SPIDER (Spatial Planning and Interactive Environment for Research) for planning the layout of custom VLSI circuits. Some of the algorithms used are technology independent while others are specific to ISL (integrated Schottky Logic) technology. Thus, in the case of ISL, a close match between the layout tool, the design style and the technology is possible. The ISL dependent portions of SPIDER are insulated from the technology independent portions. The planning tool provides estimates of the chip area, the interconnection wiring space between the function blocks and a floor plan indicating the relative placement of the function blocks. An overview of SPIDER which outlines the overall philosophy and the various tasks in chip planning, is given. Some experiments in chip planning with SPIDER are then described. Finally extensions to the scope of the planning tool are discussed. (With Raja S. Ramnarayan, PhD)

2008

The complexity of the digital electronic circuit is due to the number of gates used per system as well as the interconnection of the gates. Diminution of the total number of gates used and interconnection in the system would reduce the cost in the design, as well as increasing the efficiency of the overall system. As a result, the higher integration level, the better and the cheaper final product produced. The conventional digital circuit design method is based on Boolean algebra. There are no specific procedure to choose the right theorem or postulate for the Boolean expression simplification and it is very impractical to design the digital circuits that have more than four variable. Karnaugh map can provide the simple minimization process for Boolean expression, but it encounters difficulties when the variable is more than four. 129 4.11 The Design 3-1 Successful Chromosome Bits on GALI 130 4.12 The K-Map Solution for Design 3-1 130 4.13 4-bit Digital Circuit Structure 135 4.14 The Control Panel of the 4-Bit ODCSD 137 4.15 The Simulation Result for Design 4-1 138 4.16 The Constraint Fitness for Design 4-1 139 4.17 The Design 4-1 Successful Chromosome Set on GALI 140 4.18 Design 4-1 Successful Chromosome Bits on GALI 142 4.19 The K-Map Solution for Design 4-1 142 4.20 5-Bit Digital Circuit Structure 142 4.21 The Control Panel of the 5-Bit ODCSD 150 4.22 The Simulation Result for Design 5-1 151 4.23 The Constraint Fitness for Design 5-1 151 xix 4.24 The Design 5-1 Successful Chromosome Set on GALI 152 4.25 Design 5-1 Successful Chromosome Bits on GALI 154 4.26 Design 5-1 by using Karnaugh Minimizer 155 4.27 6-Bit Digital Circuit Structure 158 4.28 The Control Panel of the 6-Bit ODCSD 159 4.29 The Simulation Result for Design 6-1 160 4.30 The Constraint Fitness for Design 6-1 161 4.31 he Design 6-1 Successful Chromosome Set on GALI 162 4.32 Design 6-1 Successful Chromosome Bits on GALI 165 4.33 Design 6-1 by using Karnaugh Minimizer 166 4.34 The Simulation Result for the first Circuit Designed by Mentor Graphics 172 4.35 The Simulation Result for the second Circuit Designed by Mentor Graphics 173 4.36 The Simulation Result for the first Circuit Designed by Quine McCluskey 176 4.37 The Simulation Result for the second Circuit Designed by Quine McCluskey

International Journal of …, 2005

In recent years there has been a great interest in accelerating time consuming algorithms that solve large combinatorial optimization problems [1]. The advent of high density field programmable gate arrays in combination with efficient synthesis tools have enabled the production of custom machines for such difficult problems. Genetic Algorithms (GAs) [13] are robust techniques based on natural selection that can be used to solve a wide range of problems, including circuit partitioning. Although, a GA can provide very good solutions for such problems the amount of computations and iterations required for this method is enormous. As a result, software implementations of GA can become extremely slow for large circuit partitioning problems. In this paper, an architecture for implementing GAs on a Field Programmable Gate Array (FPGA) is presented. The architecture employs a combination of pipelining and parallelization to achieve substantial speedups. The GA accelerator proposed in this paper achieves more than 100× improvement in processing speed over its counterpart software implementation.

International Journal of Computer Aided Engineering and Technology, 2012

This paper describes the research and development of a computer-aided design tool which aids designers in generating printed circuit board (PCB) solutions for the manufacture of circuits using a circuit board plotter. Under computer control, a circuit board plotter produces a PCB using milling to remove copper from a copper substrate to create the desired tracks. The focus of this paper is on generating single-layer solutions as this eliminates the need for extra material handling operations which are required when milling double sided boards. The paper investigates two evolutionary algorithm approaches for optimising the track routing pattern to force a single-layer solution. The first approach optimises the order in which routes are developed. The second approach optimises both the route order and the flip rotation of the components during the routing process. Results for experiments performed on a cascaded amplifier circuit are presented.

Lecture Notes in Computer Science, 2000

We present a genetic algorithm (GA) which used a normalized postfix encoding scheme to solve the VLSI floorplanning problem. We claim to have overcome the representational problems previously associated with encoding postfix expressions into GAs, and have developed a novel encoding scheme which preserves the integrity of solutions under the genetic operators. Optimal floorplans are obtained for module sets taken from some MCNC benchmarks. The slicing tree construction procedure, used by our GA to generate the floorplans, has a run time scaling which compares very favourably with other recent approaches.

Proceedings of the 2005 conference on Genetic and evolutionary computation - GECCO '05, 2005

Simulated Evolution (SimE) is a sound stochastic approximation algorithm based on the principles of adaptation. If properly engineered it is possible for SimE to reach nearoptimal solutions in lesser time then Simulated Annealing [1], [2]. Nevertheless, depending on the size of the problem, it may have large run-time requirements. One practical approach to speed up the execution of SimE algorithm is to parallelize it. This is all the more true for multi-objective cell placement, where the need to optimize conflicting objectives (interconnect wirelength, power dissipation, and timing performance) adds another level of difficulty [3]. In this paper a distributed parallel SimE algorithm is presented for multiobjective VLSI standard cell placement. Fuzzy logic is used to integrate the costs of these objectives. The algorithm presented is based on random distribution of rows to individual processors in order to partition the solution and distribute computationally intensive tasks while efficiently traversing the complex search space. A series of experiments are performed on ISCAS-85/89 benchmarks to compare speedup with serial implementation and other earlier proposals. Discussion on comparison with parallel implementations of other iterative heuristics is included.