Visual simulator for ILP dynamic OOO processor

Facta universitatis - series: Electronics and Energetics, 2005

The usage of simulator in teaching computer architecture courses has proven to be the most acceptable way, especially when the simulators offer rich graphical and visual representation of the architecture. In this paper we present several simulators used to teach ILP (Instruction Level of Parallelism) courses. The simulators cover wide area of concepts such as internal logic organization, datapath, control, memory behavior, register renaming, branch prediction, and overall out of order execution. Special dedicated simulators cover details in internal organization like Tomasulo approach and scoreboard for organization of reservation stations. This innovative approach in laboratory exercises is used for advanced ILP course.

American Journal of Applied Sciences, 2006

The great advancement in computer architecture and cache memory design and technology had a considerable influence on the way computer architecture was taught in universities. This requires students to be able to visualize the detailed activities that take place within a computer processor and its interaction with memory system. Computer simulators could effectively be used to enhance the understanding and comprehension of cache memory operation. The main objective of this project was to design and implement a computer simulator that was used as an educational tool. This paper presents design specifications, implementation and the functional and structural components of this simulator. This allows students understand the concepts and theory of the computer hardware topics by constructing and verifying knowledge, testing and comparing several different configurations and memory access. Although there was a large number of computer simulators in the market, this simulator differs in the way it contains a specially designed assembler that feeds the simulator with the binary code. In this context it was a tool that provides a high educational value that, on one hand, helps students learn to write an error-free assembly code and on the other hand comprehend the activities that take place during the execution of the program under different settings. At the front-end of the system there are two parts; the editor and the simulator while at the back-end there are the system specially developed assembler and database.

Workshop On Computer Architecture Education, 2006

Two of the most important design issues for modern processors are power and performance. It is important for students in computer organization classes to understand the tradeoff between these two issues. This paper presents PSATSim, a graphical simulator that allows student to con- figure the design of a speculative out-of-order execution su- perscalar processor and see the effect of the

This paper proposes a new educational tool for Computer Architecture, which can provide simulation of assembly program code (instead of machine language), demonstration of several kinds of sample programs and visualization of register-transfer-level structure/behavior, namely micro-operation. Our educational tool for CPU simulation has been designed and implemented in Javascript language as Web service. Its users select simulation modes by micro step, by machine cycle and by automatic repetition of such cycles. So they can learn how a computer works graphically, recognize inner structure of CPU and understand micro-operation based behavior of CPU. Our Simulator has been also evaluated through some kinds of questionnaires by users/learners in classroom lectures. It is confirmed that the simulator has been very useful and effective to learn Computer Architecture and behav- ior/organization of CPU by means of its application.

2008

We describe the implementation of a MIPS Simulator called MIPS-SIM. MIPS-SIM is a GUI, Java-based simulator for the MIPS assembly language. MIPS, the computer architecture is widely used in industry and is the basis of the popular textbook Computer Organization and Design by David Patterson and John Hennessy, used at over 400 universities. The third edition of this text (published by Morgan Kaufmann in 2005) uses standard 32-bit MIPS as the primary teaching ISA. The MIPS-SIM simulator has been implemented for educational purposes with characteristics that are especially useful to undergraduate computer science and engineering students and their instructors who use the above textbook. MIPS-SIM should be useful in courses such as computer organization and architecture, assembly language programming, and compiler writing. MIPS-SIM implements almost the entire MIPS32 assembler-extended instruction set. MIPS-SIM also provides a simple debugger and minimal set of operating system services. We test MIPS-SIM simulator by running several MIPS assembly programs. Results prove the accuracy, correctness, effectiveness and usefulness of MIPS-SIM.

2001

Abstract: Alfa-1 is a simulated computer designed to be used in Computer Architecture and Organization courses. The DEVS formalism was used to attack the complexity of the design, allowing the definition of individual components that were later integrated into a modelling hierarchy. The goal of the toolkit is to allow the students acquiring some practice building hardware components. Here, we present the design and implementation of the tools, focusing in how to use them and how to extend the existing components. We also explain ...

ACM SIGAPL APL Quote Quad, 1989

Courses in computer architecture, among other things, must address issues of CPU design and microprogramming. Real environments, if even available, provide very specialized, vendor specific architecture solutions. Computer architecture for this reason is often approached without the benefit of any hands-on experience. Simulation obviously provides a means of exploring "new" architectures. However, simulation tools in the architecture area tend to be highly specialized, typically dictating CPU design and microprogramming organization. If engineering-level concerns of speed or timing considerations are not at issue, APL provides a uniquely effective base for building a general simulation tool to implement both mundane and exotic microprogrammable CPU designs. The authors have conceived and developed such an environment using APL. Both students and instructor can use the simulation toolkit to "implement" CPU designs or install an existing CPU architecture. The user ...

International Journal of High Speed Computing, 1999

Functional-level simulators have become an indispensable tool in designing today's processors. They help to exploit the design space and evaluate various design options so as to derive a suitable processor microarchitecture. Although Intel's x86 series processors are the most popular CPU in the computers, there are only a few simulation tools available for studying these processors. This paper introduces such a simulation tool. Internally it simulates a decoupled decode/encode architecture and has a RISC core. It is trace-driven and thus has a tracing system, a trace sampling system, and a processor simulator. We will describe the internal workings of the simulation tool and demonstrate how it can be used in evaluating a specific x86-compatible processor.

2008 38th Annual Frontiers in Education Conference, 2008

Processor implementation and performance analysis are fundamental in computer architecture education. A processor can be described at different abstraction levels: a black box with inputs and outputs, the composition of RT (Register-Transfer) level components, the composition of gate level components, etc. Performance of a processor is impacted by factors such as clock cycle, programs, and components' propagation delays. With the traditional text-based educational material, teaching and learning of the processor implementation is difficult. Processor simulation offers an effective way for education through dynamic visualization and flexible experimentation. This paper presents a MIPS32 Processor Simulator that models the single-cycle, multi-cycle, and pipeline processors described in the classic textbook, "Computer Organization and Design: The Hardware/Software Interface" written by Patterson and Hennessy. The Simulator is developed in DEVSJAVA simulator, a realization of the Discrete Event System Specification with support for modeling parallel, hierarchical, and component-based systems.

2001

Teaching computer architecture (at any level) is not an easy task. A critical mass of educators has begun using visualizations of different computer architectures based on simulators to enhance learning. Here we present three representative computer simulators for learning which show: (1) a growing consensus for computer simulation as a teaching tool for complex dynamic processes such as computer architecture and (2) one solution to meet the wide spectrum of target populations and didactic goals for teaching computer organization and architecture. The three simulators we describe are: (1) EasyCPU for the Intel 80X86 family of computer architecture, (2) Little Man Computer for a general von Neumann computer architecture and (3) RTLsim a data-path simulator for a MIPs like CPU. We discuss the additional benefits of computer simulators in terms of flexibility, financial support, obsolesence, accessibility, and research. An appendix is provided for more detailed instructions for each si...

Journal of Educational Resources in Computing, 2001

Teaching computer architecture (at any level) is not an easy task. To enhance learning, a critical mass of educators has begun using simulator visualizations of different computer architectures. Here we present three representative computer architecture simulators for learning which show that there is a growing consensus for computer simulation as a teaching tool for complex dynamic processes, such as underlying computer operations. Simulators also show the wide spectrum of pedagogical goals for teaching computer organization and architecture. Specifically, the three simulators we describe are (1) EasyCPU for the Intel 80x86 family of CPUs; (2) Little Man Computer for a general von Neumann computer architecture; and (3) RTLSim, a data path simulator for a MIPS-like CPU. An appendix is provided for more detailed descriptions of each simulator.

2000

Know-how is the most useful mean for designing new processors before a complete hardware description. The integration rate is increasing very quickly and the timeto-market has to be dramatically reduced because of the rapid evolution of technology. Therefore, reuse and rapid-prototyping are definitely a major issue to integrate existing architectures and to design new ones. SEP is an object-oriented framework which attends these problems. This paper intends to show major problems and solutions in simulation due to our simplification choices and in particular due to a not typed specification. It also presents the service feature which is a major enhancement to SEP and allow some validation of static properties about the rapidprototyped model and its associated instruction-set. In this paper some examples related to the modelling of an industrial bi-core architecture from VLSI Technologya subsidiary of Philips Semiconductors-are used to illustrate our method.

2011

We present a system that allows simulating wide range of instruction set architectures (ISA). This system includes full development and simulation environment for defining the required ISA, creating and editing assembly programs of the defined ISA, and simulating the execution of these programs. This system also includes a soft processor described in the Verilog hardware description language (HDL). This soft processor is synthesized from a customizable general processor template to implement the defined ISA on a field-programmable gate array (FPGA). This system provides an innovative, generic simulator for many architectures and for experimenting with new ones. It has a unique and easy-to-use interface that focuses on functionality rather than hardware implementation. This system was validated by successfully implementing several ISAs of various ISA classes such as MIPS, x86, and PIC. This system provides a flexible tool for teaching assembly language and computer architecture. Additionally, it provides an easily customizable soft processor that allows testing programs with real I/O interfacing circuits.

Advances in Intelligent Systems and Computing, 2014

Computer System Architecture (CSA) simulators are generally used to develop and validate new CSA designs and developments. The goal of this paper is to provide an insight into the importance of CSA simulation and the possible criteria that differentiate between various CSA simulators. Multidimensional aspects determine the taxonomy of CSA simulators including their accuracy, performance, functionality and flexibility. The Sniper simulator has been selected for a closer look and testing. The Sniper proofs its ability to scale to hundred cores with a wide range of functionality and performance.

Proceedings of the 12th European Simulation Multiconference on Simulation Past Present and Future, 1998

In order to reduce the cost, the time-to-market and to make the most pertinent choices, it becomes essential to allow designers to evaluate, very soon in the design phase, a given application performances with respect to the targetted architecture. So, we have decided to build a modelling and simulation environnement in order to evaluate digital hardware architecture performances. We considered the requisite number of cycles for processing a given application with a simple model of the architecture. In this project, we need to increase the reusability with an adjustable abstraction level. So, we decided to use object-orientation concepts to build our environnement. Then, reusing already designed components, designers will be able to build models with a level of abstraction which fit theirs goals. So, our main objective and the greatest part of out work was to define a generic object-oriented model of digital architectures. This paper mainly consists in the explanation of this model which is designed to help us to implement a visual modelling and simulation environnement.