Elements of a SystemC Design Platform

Proceedings of the eighth international workshop on Hardware/software codesign - CODES '00, 2000

Huge new design challenges for system-on-chip (SoC) are the result of decreasing time-to-market coupled with rapidly increasing gate counts and embedded software representing 50-90 percent of the functionality. The exchange of system-level intellectual property (IP) models for creating executable specifications has become a key strategic element for efficient system-to-silicon design flows. Because C and C++ are the dominant languages used by chip architects, systems engineers and software engineers today, we believe that a C-based approach to hardware modeling is necessary. This will enable co-design, providing a more natural solution to partitioning functionality between hardware and software. In this paper we present the design of SystemC, a C++ class library that provides the necessary features for modeling design hierarchy, concurrency, and reactivity in hardware. We will also describe experiences of using SystemC 1) for the coverification of 8051 processor with a bus-functional model and 2) for the modeling and simulation of an MPEG-2 video decoder.

In course of system-level design, designers need an efficient system level design language (SLDL), which can serve as the design vehicle. The complexity of the design process at this level is determined upto an extent, by the semantics and syntax definition of the SLDL being used. This report first analyzes the system-level design flow in order to establish the requirements on an SLDL. It then compares SpecC and SystemC, the two popular SLDLs, in terms of the extent they meet these requirements. Finally, it provides the essential modeling guidelines for both the SpecC and SystemC users for the cases where the constructs or the features of the respective languages give rise to an ambiguous design.

Design Automation for Embedded Systems, 2004

There is a clear need for new methodologies supporting efficient design of embedded systems on complex platforms implementing both hardware and software modules. Software development has to be carried out under a closer relationship with the underlying platform. The current trend is towards an increasing embedded software development effort under more stringent time-to-market requirements. As a consequence, it is necessary to reduce software generation cost while maintaining reliability and design quality. In that context, languages centered on describing whole systems, with software and hardware parts, have been proposed. Among these, SystemC is gaining increasing interest as a specification language for embedded systems. SystemC supports the specification of the complete system and the modeling of the platform. In this paper, the application of SystemC to performance analysis and embedded software generation is discussed. A single-source approach is proposed, that is, the use of the same code for system-level specification and profiling, and, after architectural mapping, for HW/SW co-simulation and embedded software generation. A design environment based on C++ libraries for performance analysis and software generation is presented. This approach avoids working on intermediate formats and translators, which facilitates the designer’s interaction with the system description throughout the development process. Additionally, it ensures the preservation of the computational models used for the system specification during architectural mapping and compilation.

2002

A well-defined design methodology supported by a system-level design language (SLDL) is the key for managing the complexity of the design flow, especially at the system level. Only with well-defined and unambiguous models and transformations can we achieve productivity gains through synthesis, verification and tool interoperability. This paper presents the SpecC system design language. After a general overview of SLDL requirements, it describes the SpecC language as an example of a language specifically developed to support a formalized design flow. This is the first paper in a two-part series. This part introduces the SpecC model and the SpecC language.

2002

A well-defined design methodology supported by a system-level design language (SLDL) is the key for managing the complexity of the design flow, especially at the system level. Only with well-defined and unambiguous models and transformations can we achieve productivity gains through synthesis, verification and tool interoperability. This paper presents the SpecC system design methodology. It shows how, through gradual, stepwise refinement, a design is taken from specification down to implementation. Finally, it introduces a design example of industrial-strength that has been implemented following the methodology, including the results and productivity gains achieved. This is the second paper in a two-part series. This part covers the SpecC methodology and its application to an industrial design example, a GSM vocoder.

Extended Abstract -

2004

A specification methodology for embedded system design should provide a capacity for heterogeneous specification. This would give the designer an effective tool to build a specification with different expressiveness needs, required by the multidisciplinary character of embedded systems, which, in turn, is due to their wide range of applications and an increasing integration capability. This specification methodology should be suitable for design tasks in order to improve design productivity. In this context, this paper deals with the general solution of the system-level heterogeneous specification in the framework of a specification methodology based on SystemC. This specification methodology is suitable for system-level modeling, but also for design procedures such as system-level profiling and single-source generation. Specifically, we study and propose a solution for a system-level SystemC specification which combines several untimed models of computations, (MoCs), namely CSP, PN and KPN. In order to situate clearly the heterogeneous specification methodology we will use a general study framework called Rugby metamodel.

The current trend in embedded system design is towards an increasing percentage of the embedded SW development cost of the total embedded system design costs. There is a clear need of reducing SW generation cost while maintaining reliability and design quality. SystemC represents a step forward in ensuring these goals. In this chapter, the application of SystemC to embedded SW generation is discussed. The state of art of the existing techniques for SW generation is analyzed and their advantages and drawbacks presented. In addition, methods for systematic embedded software generation which reduce the software generation cost in a platform based HW/SW co-design methodology for embedded systems based on SystemC is presented. SystemC supports a single-source approach, that is, the use of the same code for system level specification and verification, and, after HW/SW partitioning, for HW/SW co-simulation and embedded SW generation.

Computer Systems: Architectures, Modeling, …, 2004

The SystemC language plays an increasingly important role in the system-level design domain, facilitating designers to start with modeling and simulating system components and their interactions in the very early design stages. This paper presents the SCPEx language which is built on top of SystemC and which extends SystemC's programming model with a message-passing paradigm. SCPEx's message-passing paradigm raises the abstraction level of SystemC models even further, thereby reducing the modeling effort required for developing the (transaction-level) system models applied in the early design stages as well as making the modeling process less prone to programming errors. Moreover, SCPEx allows for performing automatic and transparent gathering of various simulation statistics, such as statistics on communication between components.

Electronic Chips & Systems Design Languages, 2001

Abstract We propose a new specification environment for system-level design called ECL. It combines the Esterel and C languages to provide a more versatile means for specifying heterogeneous designs. It can be viewed as the addition to C of explicit constructs from ...