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Objective of this paper is to present historiography of logic switching circuits. The research mainly focuses on chronological development and application of logic in the field of electronic and computer applications. This paper briefly discussed on the basic needs of logic synthesis and also discuss few interesting facts and design consideration regarding logic synthesis. It also enhances student’s deep understanding of different logic function minimization technique during a lecture and practical implementation.
The foundations for the design of digital logic circuits were established in the preceding chapters. The elements of Boolean algebra (two-element " switching algebra ") and how the operations in Boolean algebra can be represented schematically by means of gates (primitive devices) were presented in Chapter 2. How switching expressions can be manipulated and represented in different ways was the subject of Chapter 3, which also presented various ways of implementing such representations in a variety of circuits using primitive gates. With all of the tools for the purpose now in hand, we will be concerned in this chapter with the design of more complex logic circuits. Circuits in which all outputs at any given time depend only on the inputs at that time are called com-binational logic circuits. The design procedures will be illustrated with important classes of circuits that are now universal in digital systems. The approach taken is to examine the tasks that a combinational logic circuit is intented to perform and then identify one or more circuits that can perform the task. One circuit may have some specific advantages over others, but it may also have certain deficiencies. Often one factor can be improved, but only at the expense of others. Some important factors are speed of operation, complexity or cost of hardware, power dissipation, and availability in prefabricated units. We will take up a number of different operations that are useful in different contexts and show how appropriate circuits can be designed to carry out these operations.
Power dissipation is the major aspect which is effecting the digital circuits. By implementing the self resetting logic to the digital circuit, the power dissipation is drastically reduced. In the VLSI Design this low power technique is very advanced for DSP applications. The dynamic circuits are becoming increasingly popular because of the speed advantage over static CMOS logic circuits; hence they are widely used today in high performance and low power circuits. Self-resetting logic is a commonly used piece of circuitry that can be found in use with memory arrays as word line drivers. Self resetting logic implemented in dynamic logic families have been proposed as viable clock less alternatives. The combinational logic is a type of digital logic which is implemented by Boolean circuits, where the output is a pure function of the present input only. This is in contrast to sequential logic, in which the output depends not only on the present input but also on the history of the input. In this paper mainly the self resetting logic is applied for the different combinational circuits and the analysis is done very clearly. By implementing this low power technique for different logic circuits and adders, by comparison with DYNAMIC and SRCMOS logic's power dissipation is drastically reduced up to 35% compared with CMOS logic circuits and observations are tabulated.
Proceedings of 13th International Conference on Computer and Information Technology (ICCIT 2010), 2010
A neural representation of combinational logic circuit is proposed, called ‘Logical Neural Network’ (LNN). LNN is a feed-forward neural network (NN) where the weights of the network indicate the connections of digital circuit. The logic operations of the circuit such as AND, OR, NOR etc are performed with the neurons of LNN. A modification of Simple Genetic Algorithm (mSGA) is applied to design and optimize the LNN for a given truth table. The proposed technique is experimentally studied on four bit parity checker, two bit multiplexer, two bit full adder, full subtractor, and two bit multiplier circuits. LNN is compared with conventional ‘Cell Array’ method. LNN outperforms the Cell Array method in terms of number of required gates.
IEEE Transactions on Computers, 1977
A methodology based on the theory of Boolean equations has been developed which permits a unified approach to the analysis and synthesis of combinational logic circuits. The type of circuits covered by the approach includes both the classical loopless combinational networks as well as those that contain closed feedback loops and thus have internally a sequential character. To that end, a general multiple-output circuit represented by a Mealy-type machine is studied using characteristic equations (functions) that describe its internal structure. It is shown how behavioral properties of the circuit are reflected through the solutions of these equations. Moreover, it is demonstrated that a multiple-output incompletely specified switching function is realized if a < relation is satisfied between the corresponding characteristic functions. This leads to a new unified outlook on functional decomposition as used in modular synthesis procedures. Although the building modules are allowed to be sequential circuits, it is shown under which conditions the feedback loops are redundant with respect to the realization of a given output characteristic function, and -thus the existence conditions of nondegenerate combinational circuits with loops are stated.
2012
This is the paper presenting a novel method for defining, analyzing and implementing the basic combinational circuitry with less number of ternary multiplexers. Multilplexer is used as basic building block to realize all the combinational and sequential circuitry providing complete, concise, implementation-free description of the ternary function involved. This shows the potential of VHDL modeling and simulation which can be applied to Ternary switching circuits for verifying its functionality and timing specifications. This is the method which is used in analyzing the complex ternary functions and reduction of gate count
Reversible logic has become one of the recent emerging research pursuits contributing to the field of low power dissipating circuit design in the past few years. Reversible logic find its owns applications in various fields which include quantum computing, nanotechnology, digital signal and image processing, optical computing, Low power VLSI etc., Decoders are one of the maximum essential circuit utilized in combinational logic. The whole design of combinational circuits like decoders, comparator, full adder, multiplexer are designed using Fredkin gate, CNOT, Peres gate and R-I gate which give better quantum cost when compared to other Reversible gates. The quantum cost and garbage outputs for combinational circuits in proposed designed has been compared with a previously existing design. The reversible logic circuits are designed and implemented using VHDL code and the simulation results are obtained in Xilinx ISE version 14.7.
An efficient technique of multiple input digital circuit minimizations is proposed in this paper. The proposed method is very simple and less laborious approach to determine the minimal gate count for multiple input digital switching circuits. This exact method of minimization technique provides a minimal solution based on the breaking of minterms and arrange them in adjacent groups. To avoid bulky size of the truth table for multiple input combinational circuits, a reduced truth table is proposed here and this methodology is able to reduce its present size and at least one operation per minterms. A recursive algorithm for breaking of minterms and set formation is proposed here for computer programming. A 'Set Combine Map' is also proposed here to determine the optimal solution for manual synthesis. The proposed 'Set Combine Map' will be able to overcome successfully all the problems related to Karnaugh Map simplification process for more than four inputs systems by reducing complexity arises in finding and grouping of adjacent minterms in different levels of Karnaugh Map. An efficient minimization technique for multiple inputs and multiple outputs switching system is also proposed here.
2019
The book Digital Logic Design was written to try and solve some of problems faced by students in computer engineering, computer science and electric engineering programs. In most developing countries, there is a scarcity of affordable well written books in information technology especially digital logic design. Digital computers are implemented on digital logic circuits so their design require a good knowledge of digital logic circuits. We the authors of this book are lecturers with many years of lecturing experience at universities and really know the problems faced by studying information technology. This book is organized in form of lectures from the number systems, Boolean algebra up to computer registers. This helps the students understand how a system operates. In the lectures we have included activities and self-assessment exercise to keep the student engaged and also evaluate him/her self. This book is very helpful to both full-time students, those students studying online a...
Logic gates are the fundamental components of any digital system and can be considered the "building blocks". A logic gate is a simple electric circuit consisting of two inputs and a single output. The most frequent names for logic gates are AND, OR, NOT, XOR (Exclusive or), NAND (NOT AND), and NOR. An OR logic gate begins with the provision of two electrical inputs. If one of the inputs has the value one or indicates that it is "on," then the output will also be one. In electronics, there is a type of logic gate known as an inverter or NOT gate. The report is broken up into five distinct parts or sections. The first section of this report covers the experiment's results on logic gates. They are used in the process of performing logical operations on one or more binary inputs to produce a single binary output. This article will examine the functions of the NOT, OR, and AND gates found in a logic circuit. The findings of the experiment are presented in the fourth section. The discussion, recommendations, and conclusions drawn from the results are in the last part. In a NOT gate, the input determines whether the output is true or false, and vice versa. ALTERNATIVELY, gates output a value of HIGH if either of the two inputs is. HIGH and LOW if both inputs are LOW; this type of gate is also known as an inverter. A truth table was used to validate the information of each NOT, AND, and OR integrated circuit. Knowing how to use these seven fundamental logic gates makes it much simpler to comprehend Boolean algebra and simplifies the process of conducting circuit analysis. These gates are most commonly used in the manufacture of automatic machines. Learning how to design logical circuits was made possible by utilizing gates such as NOT, AND, and OR.
2016
Reversible logic attained major height in the contemporary research interest by leaps and bounds due to its low power consumption like design specs. The reversible logic has commencing future in CMOS design, bioinformatics, optical information processing, cryptography and nano electronic circuits. On the other hand logic circuits for digital system perform a specific information processing operation. It is designed by a set of Boolean function. This manuscript presents a novel design idea namely JSM reversible logic gate & simultaneously depict the prototype of some combinational logic circuit architecture ( i.e. half adder, half-sub-tractor & 1 bit comparator) by using the reversible proposed JSM gate. Keywords-Combinational Logic, Constant Input, Garbage Output, Quantum Cost, Reversible Logic Gates.
In this paper we focus on the reduction of switching activity in combinational logic circuits. An algorithmic approach using k-map has been proposed which modifies the normal optimal solution obtained from k-map to reduce its switching activity. More than 10% reduction in switching activity has been observed using our method. The final solution gives a good trade off between cost and power consumption.
IEEE Transactions on Computers, 1994
Abstruct-Design of multiple outputs CMOS combinational gates is studied. Two techniques for minimization of multiple output functions at the switching level are introduced. These techniques are based on innovative transistor interconnection structures named Delta and Lambda networks. The two techniques can be combined together to obtain further area reductions. Different synthesis algorithms are discussed, from exhaustive enumeration to branch and bound to heuristic techniques allowing to speed up the synthesis process. Simulation results for synthesis are intrqduced to compare the different algorithms. Design examples are also provided. Electrical simulations show that the dynamic behavior of such structures is comparable to the traditional static or domino implementations (obviously the new and traditional structures have the same static behavior).
Journal of Engineering Science and Technology Review, 2018
In this paper the authors have proposed a new 3×3 reversible gate and also proposed the reversible combinational logic circuits with better optimized quantum cost, garbage outputs and delay. The proposed new reversible logic gate is used to design of reversible 1-bit comparator circuit and realization of different logic functions such as NOT, AND, NAND, OR, NOR, XOR, NXOR. The proposed new reversible logic gate is represented by quantum implementation. The quantum cost of proposed gate is 4. The quantum cost, garbage output and delay of proposed reversible 1-bit comparator circuit are 6 which is better w. r. t. previously reported results.
In the field of cryptography, optical information processing low power CMOS design and nanotechnology Reversible logic has found its applications and has become one of the promising research directions this paper presents a novel and quantum cost efficient combinational circuits for nanotechnology. This gate can work singly as a reversible full adder unit and requires only one clock cycle. The proposed gate is a universal gate in the sense that it can be used to synthesize any arbitrary Boolean functions. It has been demonstrated that the hardware complexity offered by the proposed gate is less than the existing counterparts. The proposed reversible circuits are then compared with different reversible circuits
International Journal of Bifurcation and Chaos, 2010
We report experimental results obtained with a circuit possessing dynamic logic architecture based on one of the theoretical schemes proposed by H. Peng and collaborators in 2008. The schematic diagram of the electronic circuit and its implementation to get different basic logic gates are displayed and discussed.
2019
Abstract: In this Paper we have discussed different types of logic gates (AND,OR,NOT,NAND,NOR,XOR,XNOR) and corresponding logic tables. The base of any digital computer system are logic gates or circuits which performs logical operations on chunks of information represented digitally. Logic gates work on the basis of binary digits 0 and 1.Any intelligent system with the abilities to take decision comprises of simple logic gates. This paper is an attempt to bring forth the application of digital logic gates in day to day life with some real time applications as well like burglar alarm and security system. Through the study of no. of physical sytems e.g. mechanical, optical, electrical, thermal, biological systems it can be said that modeling of any such system can be done logically with the help of a Boolean expression. Accordingly such a system can be studied mathematically. This paper is a generic effort in understanding the Boolean mathematics behind the physical system around.
IEEE Transactions on Computer-aided Design of Integrated Circuits and Systems, 1989
In order to ascertain correct operation of digital logic circuits it is necessary to verify correct functional operation as well as correct operation at desired clock rates. To ascertain correct operation at desired clock rates signal propagation delays along a set of selected paths are verified to fall within allowed limits by applying appropriate stimuli. Earlier it was suggested that an appropriate set of paths to test would he the one that includes at least one path, with maximum modeled delay, for each circuit lead or gate input. In this paper, algorithms to select such sets of paths with minimum cardinality are given. * Sartaj K. Sahni (M'79-SM'86-F'88) received the B.Tech. degree in electrical engineering from the Indian Institute of Technology, Kanpur. India, and the M.S and Ph D degrees in computer \cience from the Cornell Univenity. Ithacd, NY
2014
Abstract—This paper deals with the testable design of conservative logic ogic based sequential circuits by using two test vectors. The conservative logic based sequential circuits are built from the reversible gates. ThisReversible Reversible or information lossless circuits have extensive applications in quantum computing, optical computing, as well as ultra-low low power VLSI circuits. circuits.Theoptimized designs igns of reversible D Latch,Reversible negative enable D latch,Master slave Flip-Flop,Double edge triggered Flip-Flops and its application circuits like reversible universal shift registers, four bit binary counter are proposed.This This proposed design can identify any stuck-at-fault fault in the circuits and this proposed circuit is efficient than the conventional circuit designed using classical gate in terms of number of gate count,delay in the circuit,garbageoutput, output, power dissipation and testability.Thisproposeddesign canidentify any stuck-at-fault in the ci...
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