HOPLA - PLA Optinization and Synthesis

Proceedings of the 22nd ACM/IEEE …, 1985

This thesis investigates technical issues concerning the automated generation of highly regular VLSI circuit layouts (e.g. RAMs, PLAs, systolic arrays) that are crucial to the designability and realizability of large VLSI systems. The key is to determine the most profitable level of abstraction, which is accomplished by the introduction of true macro abstraction, interface inheritance, delayed binding, and the complete decoupling of procedural and graphical design information. These abstraction mechanisms are implemented in the Regular Structure Generator, an operational layout generator with significant advantages over first generation layout tools. Its advantages are demonstrated by a pipelined array multiplier layout example. A leaf cell compactor that can make the RSG technology transportable is also investigated.

Computer Sciences Forum (Honeywell), 1984

This article describes a chip planning tool called SPIDER (Spatial Planning and Interactive Environment for Research) for planning the layout of custom VLSI circuits. Some of the algorithms used are technology independent while others are specific to ISL (integrated Schottky Logic) technology. Thus, in the case of ISL, a close match between the layout tool, the design style and the technology is possible. The ISL dependent portions of SPIDER are insulated from the technology independent portions. The planning tool provides estimates of the chip area, the interconnection wiring space between the function blocks and a floor plan indicating the relative placement of the function blocks. An overview of SPIDER which outlines the overall philosophy and the various tasks in chip planning, is given. Some experiments in chip planning with SPIDER are then described. Finally extensions to the scope of the planning tool are discussed. (With Raja S. Ramnarayan, PhD)

IEEE Transactions on Semiconductor Manufacturing, 1995

Several yield enhancement techniques are proposed for the last two stages of VLSI design, i.e., topological/symbolic and physical layout synthesis. Our approach is based on modi cations of the symbolic/physical layout to reduce the sensitivity of the design to random point defects without increasing the area, rather than fault tolerance techniques. A layout compaction algorithm is presented and the yield improvement results of some industrial layout examples are shown. This algorithm has been implemented in a commercial CAD framework. Some routing techniques for wire length and via minimization are presented and the results of wire length reduction in benchmark routing examples are shown. We demonstrate through topological optimization for PLA-based designs that yield enhancement can be applied even at a higher level of design abstraction. Experimental results show that it is possible to achieve signi cant yield improvements without increasing the layout area by applying the proposed techniques during layout synthesis.

IEEE Transactions on Automatic Control, 1983

In this paper, we present a new methodology for custom VLSI layout which aims at a low turnaround time and a high quality of design. VLSI circuits are highly complex, and to speed up the design process we exploit the hierarchical structure of a design, splitting the problem domain into several levels. The process of layout at each level is divided into steps such as placement of rectangular blocks, determining block dimensions, determining interconnection paths, etc. In order to obtain high quality designs, we have systematically analyzed the relationship among the parameters being computed at various steps and have accordingly organized the flow of data and control through these steps. There are two novel features in our scheme. First, we do not follow the usual pure top-down or pure bottom-up approach, so as to take into account the infl.uence of design decisions at the higher levels on design decisions made at the lower levels, as well as vice versa. For example, we determine the geomehy of a block taking into consideration the context in which it is placed, as well as the geometries of the lower level blocks it encloses. Second, we perform a look-ahead operation when the values of some. parameters are needed before they are actually deterministically computable by the process. For example, at the ,time of placement, the area required for routing is estimated statistically (before doing the actual routing) so that a more routable placement can be obtained, thereby avoiding some unnecessary iterations.

ACM SIGPLAN OOPS …, 1995

When designing systems-on-a-chip (SoCs), a unique opportunity exists to generate custom FPGA architectures that are specific to the application domain in which the device will be used. The inclusion of such devices provides an efficient compromise between the flexibility of software and the performance of hardware, while at the same time allowing for postfabrication modification of the SoC. To automate the layout of reconfigurable subsystems for systems-on-a-chip, we present three alternative methods, namely Template Reduction, Circuit Generator, and Standard Cell methods. Template Reduction begins with a full-custom layout as a template that is a superset of the required resources, and removes those resources that are not needed by a given application domain. Circuit Generator takes advantage of the regularity that exists in FPGAs by using circuit generators to create the custom reconfigurable devices. Finally, Standard Cell automates the creation of circuits by using a standard cell library that has been optimized for reconfigurable devices. This paper presents algorithms for each of these approaches, and quantifies the relative quality in terms of area and delay.

2019

Programmable logic arrays (PLAs) are traditional digital electronic devices. A PLA is a simple programmable logic device (SPLD) used to implement combinational logic circuits. A PLA has a set of programmable AND gates, which link to a set of programmable OR gates to produce an output. The AND-OR layout of a PLA allows for implementing logic functions that are in a sum-of-products form. PLAs are available in the market in different types. PLAs could be stand alone chips, or parts of bigger processing systems. Stand alone PLAs are available as mask programmable (MPLAs) and field programmable (FPLAs) devices. The attractions of PLAs that brought them to mainstream engineers include their simplicity, relatively small circuit area, predictable propagation delay, and ease of development. The powerful-but-simple property brought PLAs to rapid prototyping, synthesis, design optimization techniques, embedded systems, traditional computer systems, hybrid high-performance computing systems, et...

1983

Abstract Programmable Logic Arrays are important building blocks of VLSI circuits and systems. We address the problem of optimizing the silicon area and the performances of large logic arrays. In particular we describe a general method for compacting a logic array defined as multiple row and column folding and we address the problem of interconnecting a PLA to the outside circuitry.

Integration, 1988

We develop an algorithm for covering polygons by rectangles. The algorithm achieves a minimum number of rectangles in most cases and in a short time. The algorithm is suitable for use in generating masks for microcircuits, design rule checking of VLSI layouts, graphical editors, etc.

IEE Proceedings - Circuits, Devices and Systems, 1995

In a system level or logic level design process, the decisions made during early phases of the high level design have the greatest impacts on the performance of the final chip. However, these impacts will not be realised until very late in the physical design stage. In addition, it has been observed repeatedly that the most frustrating problem in IC design is to understand the relationship between the early phase decisions and the final layout result. It is therefore important, in logic synthesis to optimise a cost function which could relate the logic equation and the final layout performance. The authors develop a logic synthesis approach which relies on an accurate design evaluation program to estimate the final design attributes such as layout area and speed. Given a candidate design implementation, an evaluation programme will be called upon to provide quick and accurate estimates of the layout area or critical path delay. This information will then be used as a feedback to the logic optimisation system. Based on this feedback, the system will 'reorient' itself toward a new direction for optimisation. Such a scheme represents a more realistic way of generating optimal layout implementations. m c IEE, 1995 Paper 19256 (ElO), first received 15th September 1994 and in revised form 27th February 1995 Y . Chen is with the Hitachi