Optically programmable gate array

Optics in Computing 2000, 2000

The Optically Programmable Gate Array (OPGA), an optical version of a conventional FPGA, benefits from a direct parallel interface between an optical memory and a logic circuit. The OPGA utilizes a holographic memory accessed by an array of VCSELs to program its logic. An active pixel sensor array incorporated into the OPGA chip makes it possible to optically address the logic in a very short time allowing for rapid dynamic reconfiguration. Combining spatial and shift multiplexing to store the configuration pages in the memory, the OPGA module can be made compact. The reconfiguration capability of the OPGA can be applied to solve more efficiently problems in pattern recognition and database search.

SPIE Proceedings, 1999

Reconfigurable processors bring a new computational paradigm where the processor modifies its structure to suit a given application, rather than having to modify the application to fit the device. The Optically Programmable Gate Array, an enhanced version of a conventional FPGA, utilizes a holographic memory accessed by an array of VCSELs to program its logic. Combining spatial and shift multipexing to store the configuration pages in the memory, the OPGA module is very compact and has extremely short configuration time allowing for dynamic reconfiguration. The reconfiguration capability of the OPGA can be applied to solve more efficiently problems in pattern recognition and digit classification.

1999

We have developed an optically reconfigurable field programmable gate array (OFPGA). The OFPGA integrated circuit is designed for high-speed configuration in systems based on a reconfigurable computing paradigm [1]. In these environments, the computation resources provided by the FPGA reused in multiple configurations throughout a single application program. Example applications are image and signal processing, data compression and database operations. In these applications, the same FPGA could be used to perform floating-point operations, histogramming, and query processing .

proceedings of IEEE …, 2004

In the last three years there were distinguished advancements in designing and implementing our optical setup of Cellular Neural Networks (CNNs), Programmable Optical Array Computer (POAC), which we try to show milestones through its evolution. Firstly, the Bacteriorhodopsin as an embedded holographic memory of the system is reviewed. Secondly, several previous architecture versions of POAC are compared. Finally, the present optical template library is presented.

Applied Optics, 1988

Regular free-space interconnects such as the perfect shuffle and banyan provided by beam splitters, lenses, and mirrors connect optical logic gates arranged in 2-D arrays. An algorithmic design technique transforms arbitrary logic equations into a near-optimal depth circuit. Analysis shows that an arbitrary interconnect makes little or no improvement in circuit depth and can even reduce throughput. Gate count is normally higher with a regular interconnect, and we show cost bounds. We conclude that regularly interconnected circuits will have a higher gate count compared with arbitrarily interconnected circuits using the design techniques presented here and that regular free-space interconnects are comparable with arbitrary interconnects in terms of circuit depth and are preferred to arbitrary interconnects for maximizing throughput. 1. Introduction All-optical digital computers have the potential for high speed, cheap communications, and massive parallelism. Logic gates based on nonlinear dielectric constants were investigated theoretically in the early 1960s by von Neumann. 1 In the last few years optical bistable devices, 2 ' 3 nonlinear Fabry-Perots, 4 ' 5 and hybrid electrooptic devices 6 have been studied experimentally. These results encourage development of architectures suitable for optics. Historically, two architectural approaches have dominated the field. One approach uses integrated optics to interconnect optical logic devices. A system designed with this approach is architecturally similar to a conventional computer, with logic gates connected in arbitrary configurations. This similarity means that an optical computer designed with this approach is worth building only if it can be made more cheaply or more powerful. An alternative approach makes use of 2-D arrays of devices interconnected in free space. This approach uses space-variant interconnects (provided by holograms) or space-invariant regular interconnects (provided by beam splitters). We prefer the space-invariant regular interconnect approach for simplicity, extensibility, and high throughput. To take advan

Bacteriorhodopsin has been proved to be an outstanding candidate for reversible, transient, real-time, holographic material. Here we show our preliminary experimental investigation of its applicability as a transient analog memory, concentrating on its possible utilization in optical CNN implementations and in programmable opto-electronic analogic CNN computers (POAC). Different possible architectures and the technical details of its applicability are also discussed. The main objective is to provide a framework for the implementation of Programmable Opto-Electronic Analogic CNN Computers embedding CNN Universal Chips. Specifically, a new method for optical CNN implementation is provided and some details are experimentally studied. The POAC architecture includes the integration of an optical processing system, such as a joint transform correlator using bacteriorhodopsin as holographic material, with the fast spatio-temporal processing capabilities of a CNN-UM chip. We have built and tested an optical sub-unit of this experimental opto-electronic architecture to examine their processing capabilities in complex target recognition tasks. The main idea is to introduce stored programmability into optical computing. The specification of the necessary holographic material for POAC application is given. Some measurement results on BR samples are presented.

Applied Optics, 1995

The slow execution speed of current rule-based systems 1RBS's2 has restricted their application areas. To improve the speed of RBS's, researchers have proposed various electronic multiprocessor systems as well as optical systems. However, the electronic systems still suffer in performance from the large amount of required time-consuming pattern-matching and comparison operations at the core of RBS's. And optical systems do not fully exploit the available parallelism in RBS's. We propose an optical contentaddressable parallel processor for expert systems. The processor executes the three basic RBS operations, match, select, and act, in a highly parallel fashion. Additionally, it extracts and exploits all possible parallelism in a RBS. Distinctive features of the proposed system include the following: 112 two-dimensional representation of data 1knowledge2 and control information to exploit the parallelism of optics in the three RBS units; 122 capability of processing general-domain knowledge expressed in terms of variables, numbers, symbols, and comparison operators such as greater than and less than; 132 the parallel optical match unit, which performs the two-dimensional optical pattern matching and comparison operations; 142 a novel conflict-resolution algorithm to resolve conflicts in a single step within the optical select unit. The three units and the general-knowledge representation scheme are designed to make the optical content-addressable parallel processor for expert systems suitable for any high-speed general-purpose RBS.

The computation capacity of conventional FPGAs is directly proportional to the size and expressive power of Look Up Table (LUT) resources. Individual LUT performance is limited by transistor switching time and power dissipation, defined by the CMOS fabrication process. In this paper we propose OLUT, an optical core implementation of LUT, which has the potential for low latency and low power computation. In addition, the use of Wavelength Division Multiplexing (WDM) allows parallel computation, which can further increase computation capacity. Preliminary experimental results demonstrate the potential for optically assisted on-chip computation.

Photonic Devices and Algorithms for Computing IV, 2002

A major research area is the representation of knowledge for a given application in a compact manner such that desired information relating to this knowledge is easily recoverable. A complicated procedure may be required to recover the information from the stored representation and convert it back to usable form. Coder/decoder are the devices dedicated to that task. In this paper the capabilities that an Optical Programmable Logic Cell offers as a basic building block for coding and decoding are analyzed. We have previously published an Optically Programmable Logic Cells (OPLC), for applications as a chaotic generator or as basic element for optical computing. In optical computing previous studies these cells have been analyzed as full-adder units, being this element a basic component for the arithmetic logic structure in computing. Another application of this unit is reported in this paper. Coder and decoder are basic elements in computers, for example, in connections between processors and memory addressing. Moreover, another main application is the generation of signals for machine controlling from a certain instruction. In this paper we describe the way to obtain a coder/decoder with the OPLC and which type of applications may be the best suitable for this type of cell.

Applied Optics, 1984

A general technique is described for implementing sequential logic circuits optically. In contrast with semiconductor integrated circuitry, optical logic systems allow very flexible interconnections between gates and between subsystems. Because of this, certain processing algorithms which do not map well onto semiconductor architectures can be implemented on the optical structure. The algorithms and processor architectures which can be implemented on the optical system depend on the interconnection technique. We describe three interconnection methods and analyze their advantages and limitations.