Design Considerations for Single-Chip Computers of the Future

2012

This paper starts from the programmer’s view and states architectural principles for designing the onechip many processor computer. John Backus’s and Gary Sabot’s old visions about how a parallel computer must be programmed are followed in the context of the current technologies. The proposed architectural principles are exemplified with the Connex chip, a 1024-cell SPMD engine able to provide 120 GOPS/Watt, 6 GOPS/mm2 and 60 GOPS/$. Key–Words: Parallel computation, computer architecture, parallel programming, functional programming, manycell computer.

Third Caltech Conference on Very Large Scale Integration, 1983

Current VLSI fabrication technology makes it possible to design a 32-bit CPU on a single chip. However, to achieve high performance from that processor, the architecture and implementation must be carefully designed and tuned. The MIPS processor incorporates some new architectural ideas into a single-chip, nMOS implementation. Processor performance is obtained by the careful integration of the software (e.g., compilers), the architecture, and the hardware implementation. This integrated view also simplifies the design, making it practical to implement the processor at a university.

Proceedings of the International Symposium on Memory Systems, 2018

This paper presents the notion of a monolithic computer, a future computer architecture in which a CPU and a high-capacity main memory system are integrated in a single die. Such computers will become possible in the near future due to emerging non-volatile memory technology. In particular, we consider using resistive random access memory, or ReRAM, from Crossbar Incorporated. Crossbar's ReRAM is dense, fast, and consumes zero static power. Also, it can be fabricated in a standard CMOS logic process, allowing it to be integrated into a CPU's die. The ReRAM cells are manufactured in between metal wires and do not employ per-cell access transistors, so the bulk of the transistors underneath the ReRAM arrays are vacant. This means a CPU can be implemented using a die's logic transistors (minus transistors for access circuits), while the ReRAM can be implemented "in the wires" above the CPU. This will enable massive memory parallelism, as well as high performance and power efficiency. We discuss several challenges that must be overcome in order to realize monolithic computers. First, there is a physical design challenge of merging ReRAM access circuits with CPU logic. Second, while Crossbar's ReRAM technology exists today, it is currently targeted for storage. There is a device challenge to redesign Crossbar's ReRAM so that it is more optimized for CPUs. And third, there is an architecture challenge to expose the massive memory-level parallelism that will be available in the on-die ReRAM. This will require highly parallel network-on-chip and memory controller designs, and a CPU architecture that can issue memory requests at a sufficiently high rate to make use of the memory parallelism. 1 INTRODUCTION The primary means by which computer hardware improves is via increased integration due to Moore's Law scaling. Over the years, Moore's Law has provided a steady improvement in computer hardware, but along the way, there have been notable points of disruptive

the objective of this paper is to provide an overview on the present state of design technology for SoC. Attempt has been made to capture the basic issues regarding SoC design the paper describes the SoC components explores present day architecture of SoC and the issues involved in the SoC design process. SoC design offers many advantages, there are still the familiar challenges of designing a complex system, now on a chip. The ever-shortening time-to-market compounds these challenges. Without a major advance in productivity, designers will be able to consider only a very few highlevel system designs and will have to limit their product differentiation to the software running on a standard embedded processor.

Microelectronics Journal, 1984

1he trend in modem hardware design (especially in that of processors) has been away from unsophisticated designs, and towards the implementation of highly functional systems. However, there are still some applications for which unrefined systems have a place. In these, ease of using the device is sacrificed for small physical size. Often there is a need to be able to insert an "extra" processor into a small space (for instance on a memory chip); the need for high yields from a wafer of semiconductor is another possible reason for requiring such a small processor, this time as a stand-alone device. This report describes the design of a simple sixteen bit processor which uses only 600 transistors in its implementation. Understandably, the power of the processor, the "NVDAC', is very limited. However, this report sets out to demonstrate that many of the savings have been made by optimising the usa of the hardware which is provided, and that the resultant design has more power than its small size would suggest.

2020

I present the design and evaluation of two new processing elements for reconfigurable computing. I also present a circuitlevel implementation of the data paths in static and dynamic design styles to explore the various performance-power tradeoffs involved. When implemented in IBM 90-nm CMOS process, the 8-b data paths achieve operating frequencies ranging over 1 GHz both for static and dynamic implementations, with each data path supporting single-cycle computational capability. A novel single-precision floating point processing element (FPPE) using a 24-b variant of the proposed data paths is also presented. The full dynamic implementation of the FPPE shows that it operates at a frequency of 1 GHz with 6.5-mW average power consumption. Comparison with competing architectures shows that the FPPE provides two orders of magnitude higher throughput. Furthermore, to evaluate its feasibility as a soft-processing solution, we also map the floating point unit onto the Virtex 4 and 5 devices, and observe that the unit requires less than 1% of the total logic slices, while utilising only around 4% of the DSP blocks available. When compared against popular fieldprogrammable-gate-array-based floating point units, our design on Virtex 5 showed significantly lower resource utilisation, while achieving comparable peak operating frequency. 3D integration of solid-state memories and logic, as demonstrated by the Hybrid Memory Cube (HMC), offers major opportunities for revisiting near-memory computation and gives new hope to mitigate the power and performance losses caused by the "memory wall". Several publications in the past few years demonstrate this renewed interest. In this paper we present the first exploration steps towards design of the Smart Memory Cube (SMC), a new Processor-in-Memory (PIM) architecture that enhances the capabilities of the logic-base (LoB) die in HMC. An accurate simulation environment called SMCSim has been developed, along with a full featured software stack. The key contribution of this work is full system analysis of near memory computation including high-level software to low-level firmware and hardware layers, considering offloading and dynamic overheads caused by the operating system (OS), cache coherence, and memory management. A zero-copy pointer passing mechanism has been devised to allow low overhead data sharing between the host and the PIM. Benchmarking results demonstrate up to 2X performance improvement in comparison with the host System-on-Chip (SoC), and around 1.5X against a similar host-side accelerator. Moreover, by scaling down the voltage and frequency of PIM's processor it is possible to reduce energy by around 70 % and 55 % in comparison with the host and the accelerator, respectively.

Computer, 2005

Multiprocessor Systemson-Chips requirements and implementation constraints push developers to build custom, heterogeneous architectures. The applications that SoC designs target exhibit a punishing combination of constraints: • not simply high computation rates, but realtime performance that meets deadlines; • low power or energy consumption; and • low cost. Each of these constraints is difficult in itself, but the combination is extremely challenging. And, of course, while meeting these requirements, we can't break the laws of physics. MPSoCs balance these competing constraints by adapting the system's architecture to the application's requirements. Putting computational power where it is needed meets performance constraints; removing unnecessary elements reduces both energy consumption and cost. MPSoCs are not chip multiprocessors. Chip multiprocessors are components that take advantage of increased transistor densities to put more processors on a single chip, but they don't try to leverage application needs. MPSoCs, in contrast, are custom architectures that balance the constraints of VLSI technology with an application's needs. Single processors may be sufficient for low-performance applications that are typical of early microcontrollers, but an increasing number of applications require multiprocessors to meet their performance goals.

2000

Looking into the future, when the billion transitor ASICs will become reality, this paper presents Network on a chip (NOC) concept and its associated methodology as solution to the design productivity problem. NOC is a network of computational, storage and I/O resources, interconnected by a network of switches. Resources communcate with each other using addressed data packets routed to their destination by the switch fabric. Arguments are presented to justify that in the billion transistor era, the area and performance penalty would be minimum. A concrete topology for the NOC, a honeycomb structure, is proposed and discussed. A methodology to support NOC is presented. This methodology outlines steps from requirements down to implementation. As an illustration of the concepts, a plausible mapping of an entire basestation on hypothetical NOC is discussed.

J. Embed. Comput., 2006

Nowadays and future embedded and special purpose systems need a qualitative step forward in the research efforts better than continue in quantitatively improve the designs: it’s time for scaling-out architectures, instead of scaling-up frequency. As transistor count is still increasing as expected by Moore’s law, recent challenges like wire-delay, design complexity, and power requirements are becoming more and more important. These problems are preventing the evolution of chip architecture in the directions followed in the previous decades, when clock frequency as well could scale-up with Moore’s law. Many researchers and companies have started to look at building multiprocessors on a single chip, following both past and novel design solutions: no doubt that we are all expecting several cores on a single chip in the near future. Such single-chip architectures are also expected to have full success in the embedded domain. In this case, application specific requirements would also dem...

Proceedings of ASP-DAC'95/CHDL'95/VLSI'95 with EDA Technofair, 1995