Using SAT-Based Techniques in Test Vectors Generation

2010

Dynamic burn-in testing is an integral component of any test plan that seeks to produce reliable integrated circuits. Despite its importance in ensuring the reliability of semiconductors, burn-in has been a major contributor to overall test cost and turnaround time. In this work we discuss the application of advanced Boolean satisfiability (SAT) techniques to generate a set of vectors or input stimuli that increases the nodal activity in the circuit and hence the elevation of its temperature. The vectors are designed to uniformly stress all parts of the circuit. Additionally, we present a SAT-based methodology where weak nodes can selectively be targeted for high switching activity in an effort to detect potential failures. Finally, SAT-based solvers are compared against generic Integer Linear Programming (ILP) solvers when handling the vector generation problem.

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1992

This article describes the Boolean satisfiability method for generating test patterns for single stuck-at faults in combinational circuits. This new method generates test patterns in two steps: First, it constructs a formula expressing the Boolean diference between the unfaulted and faulted circuits. Second, it applies a Boolean satisjiability algorithm to the resulting formula. This approach differs from previous methods now in use, which search the circuit structure directly instead of constructing a formula from it. The new method is general and effective: it allows for the addition of heuristics used by structural search methods, and it has produced excellent results on popular test pattern generation benchmarks.

2011 Design, Automation & Test in Europe, 2011

Fault simulation of digital circuits must correctly compute fault coverage to assess test and product quality. In case of unknown values (X-values), fault simulation is pessimistic and underestimates actual fault coverage, resulting in increased test time and data volume, as well as higher overhead for designfor-test. This work proposes a novel algorithm to determine fault coverage with significantly increased accuracy, offering increased fault coverage at no cost, or the reduction of test costs for the targeted coverage. The algorithm is compared to related work and evaluated on benchmark and industrial circuits.

2008

A method is presented for deterministic test pattern generation using a uniform functional fault model for combinational circuits. The fault model allows to represent the physical defects in components and defects in the communication network of components by the same technique. Physical defects are modeled as parameters in generic Boolean differential equations. Solutions of these equations give the conditions at which defects are locally activated. The defect activation conditions are used as functional fault models for logic level test generation purposes. A method is proposed which allows to find the types of faults that may occur in a real circuit and to determine their probabilities. A defect-oriented deterministic test generation tool was developed, and the experimental data obtained by the tool for ISCAS'85 benchmarks are presented. It was shown that for the majority of cases 100% stuck-at fault tests do not cover 100% of the physical defects. The main feature of the new tool is that it allows to reach 100% coverage for the given set of defects or to prove the redundancy of not detected defects. Shorts are the dominant cause of faults in modern CMOS processes. In current approach the wired-AND fault model was considered.

A method is presented for deterministic test pattern generation using a uniform functional fault model for combinational circuits. The fault model allows to represent the physical defects in components and defects in the communication network of components by the same technique. Physical defects are modeled as parameters in generic Boolean differential equations. Solutions of these equations give the conditions at which defects are locally activated. The defect activation conditions are used as functional fault models for logic level test generation purposes. A method is proposed which allows to find the types of faults that may occur in a real circuit and to determine their probabilities. A defect-oriented deterministic test generation tool was developed, and the experimental data obtained by the tool for ISCAS'85 benchmarks are presented. It was shown that for the majority of cases 100% stuck-at fault tests do not cover 100% of the physical defects. The main feature of the new...

1993

This paper presents new cost-effective heuristics for the generation of minimal test sets. Both dynamic techniques, which are introduced into the test generation process, and a static technique, which is applied to already generated test sets, are used. The dynamic compaction techniques maximize the number of faults that a new test vector detects out of the yet-undetected faults as well as out of the already-detected ones. Thus, they reduce the number of tests and allow tests generated earlier in the test generation process to be dropped. The static compaction technique replaces N test vectors by M < N test vectors, without loss of fault coverage. During test generation, we also find a lower bound on test set size. Experimental results demonstrate the effectiveness of the proposed techniques.

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1990

A sequence of input vectors which detects all transistor stuck-open faults in a CMOS combinational circuit is a complete test sequence. Given a complete set of two-pattern tests for transistor stuckopen faults in a C M O S circuit, we show that a complete test sequence of minimum length can be obtained efficiently.

To cope with the problems of technology scaling, a robust design has become desirable. Self-checking circuits combined with rollback or repair strategies can provide a low cost solution for many applications. However, standard synthesis procedures may violate design constraints or lead to sub-optimal designs. The SAT-based strategies for the verification and synthesis of self-checking circuits presented in this paper can provide efficient solutions.

2007

Due to the rapidly growing speed and the decreasing size of gates in modern chips, the probability of faults caused by the production process grows. Already small variations lead to functional failures. Therefore, dynamic fault models like the Path Delay Fault Model (PDFM) have become more important in the last years. At the same time, classical algorithms for test pattern generation reach their limits due to the steadily increasing complexity of modern circuits.

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2019

As the complexity of digital designs continuously increases, existing methods to ensure their correctness are facing more serious challenges. Although many studies have been provided to enhance the efficiency of debugging methods, they are still suffering from the lack of scalable automatic correction mechanisms. In this paper, we propose a method for correcting multiple design bugs in gate level circuits. To reduce the correction time, an incremental satisfiability based mechanism is proposed which not only does not require a complete set of test patterns to produce a gate level implementation which does not exhibit erroneous behavior, but also will not reintroduce old bugs after fixing new bugs. The results show that our method can quickly and accurately suggest corrected gates even for large industrial circuits with many bugs. Average improvements in terms of the runtime and memory usage in comparison with existing methods are 2.8× and 6.5×, respectively. Also, the results show that our method compared to the state-of-the-art methods needs 2.6× less test patterns.