An LDPC decoding algorithm utilizing early decisions

Proc. Swedish System-on-Chip …, 2005

Low-density parity-check codes have recently received extensive attention as a forward error correction scheme in a wide area of applications. The decoding algorithm is inherently parallelizable, allowing communication at high speeds. One of the main disadvantages, however, is large memory requirements for interim storing of decoding data. In this paper, we investigate a modification to the decoding algorithm, using early decisions for bits with high reliabilities. Currently, there are two early decision schemes proposed. We compare their theoretical performances and their suitability for hardware implementation. We also propose a new decision method, which we call weak decisions, that offers an increase in performance by a factor of two.

International Journal of Computing and Digital Systemss

This paper presents Verilog implementation of Low-Density Parity-Check (LDPC) decoders using Sum-Product and Min-Sum algorithms which will take more area as compared to other decoding algorithms. In this paper, area efficient LDPC decoder depending upon abridged complexity Minsum algorithm is presented. It reduces the permutational complexity with limiting the extrinsic information bit length to 4 bits and it modifies the check and variable node processing operation. Compilation at an algorithmic level explains that the proposed decoder attain good error performance as compared to a Sum Product Algorithm based decoder, and consequently handles the problem of immense error performance deprivation of a LDPC decoder. A Min Sum Based LDPC decoder with a matrix length (1000, 500) has been implemented in a MATLAB with a 10-1 BER and the design is implemented in HDL Verilog. The complete top level module was done by structural modeling style and simulated with SPARTAN FPGA Family. The percentage saving in area is about 33% of slices and provides a throughput of 1.46Gbps.

Low Density Parity Check (LDPC) codes are one of the block coding techniques that can approach the Shannon's limit within a fraction of a decibel for high block lengths. In many digital communication systems, these codes have strong competitors of turbo codes for error control. LDPC codes performance depends on the excellent design of parity check matrix and many diverse research methods have been used by different study groups to evaluate the performance. Unlike many other classes of codes, LDPC codes are already equipped with a fast, probabilistic decoding algorithm. This makes LDPC codes not only attractive from a theoretical point of view, but also very suitable for practical applications. This paper throws hard decision and soft decision algorithm of LDPC. The hard decision algorithm contains Bit flipping algorithm and Soft decoding algorithm contains Sum product algorithm which is used to correct burst error. Sum Product algorithm is also called as belief propagation. Bit ...

International Journal of Electrical and Computer Engineering (IJECE), 2023

It is proved that hard decision algorithms are more appropriate than a soft decision for low-density parity-check (LDPC) decoding since they are less complex at the decoding level. On the other hand, it is notable that the soft decision algorithm outperforms the hard decision one in terms of the bit error rate (BER) gap. In order to minimize the BER and the gap between these two families of LDPC codes, a new LDPC decoding algorithm is suggested in this paper, which is based on both the normalized min-sum (NMS) and modified-weighted bit-flipping (MWBF). The proposed algorithm is named normalized min sum-modified weighted bit flipping (NMSMWBF). The MWBF is executed after the NMS algorithm. The simulations show that our algorithm outperforms the NMS in terms of BER at 10-8 over the additive white gaussian noise (AWGN) channel by 0.25 dB. Furthermore, the proposed NMSMWBF and the NMS are both at the same level of decoding difficulty.

2015

“Low Density” comes from the characteristic of their parity-check matrix that contains small number of 1’s in comparison to the amount of 0’s in them. This sparseness of parity check matrix guarantees two features: First, ‘a decoding complexity’ which increases only linearly with the code length and second, ‘a minimum distance’ which also increases linearly with the code length. These codes are practical implementation of Shannon noisy coding theorem[1]. LDPC codes are similar to other linear block codes. Actually, every existing code can be successfully implemented with the LDPC iterative decodSukhleen Bindra Narang, Kunal Pubby*, Hashneet Kaur Department of Electronics Technology, Guru Nanak Dev University, Amritsar, (INDIA) E-mail: [email protected]

EURASIP Journal on Wireless Communications and Networking, 2014

A word error rate (WER) reducing approach for a hybrid iterative error and erasure decoding algorithm for low-density parity-check codes is described. A lower WER is achieved when the maximum number of iterations of the min-sum belief propagation decoder stage is set to certain specific values which are code dependent. By proper choice of decoder parameters, this approach reduces WER by about 2 orders of magnitude for an equivalent decoding complexity. Computer simulation results are given for the efficient use of this hybrid decoding technique in the presence of additive white Gaussian noise.

In this paper, a reduced-complexity, scalable implementation of LDPC decoder is presented. The decoder architecture in this paper is an improved version of . The new architecture makes the implementation of multiple code rates, multiple block sizes and multiple standards LDPC decoder very straightforward. As an example, we implemented a parameterized decoder that supports the LDPC code in IEEE 802.16e standard, which requires code rates of 1/2, 2/3 and 3/4, with block sizes varying from 576 to 2304. The decoder is synthesized with Texas Instruments' 90 nm ASIC process technology, with a target operation frequency of 100 MHz, 15 decoding iterations, the maximum data rate is up to 256 Mbps.

IJSCA, 2011

Low Density Parity Check (LDPC) code approaches Shannon-limit performance for binary field and long code lengths.

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

This paper introduces a new approach to costeffective, high-throughput hardware designs for Low Density Parity Check (LDPC) decoders. The proposed approach, called Non-Surjective Finite Alphabet Iterative Decoders (NS-FAIDs), exploits the robustness of message-passing LDPC decoders to inaccuracies in the calculation of exchanged messages, and it is shown to provide a unified framework for several designs previously proposed in the literature. NS-FAIDs are optimized by density evolution for regular and irregular LDPC codes, and are shown to provide different trade-offs between hardware complexity and decoding performance. Two hardware architectures targeting high-throughput applications are also proposed, integrating both Min-Sum (MS) and NS-FAID decoding kernels. ASIC post synthesis implementation results on 65nm CMOS technology show that NS-FAIDs yield significant improvements in the throughput to area ratio, by up to 58.75% with respect to the MS decoder, with even better or only slightly degraded error correction performance.

—Various log-likelihood-ratio-based belief-propagation (LLR-BP) decoding algorithms and their reduced-complexity derivatives for low-density parity-check (LDPC) codes are presented. Numerically accurate representations of the check-node update computation used in LLR-BP decoding are described. Furthermore, approximate representations of the decoding computations are shown to achieve a reduction in complexity by simplifying the check-node update, or symbol-node update, or both. In particular, two main approaches for simplified check-node updates are presented that are based on the so-called min-sum approximation coupled with either a normalization term or an additive offset term. Density evolution is used to analyze the performance of these decoding algorithms, to determine the optimum values of the key parameters, and to evaluate finite quantization effects. Simulation results show that these reduced-complexity decoding algorithms for LDPC codes achieve a performance very close to that of the BP algorithm. The unified treatment of decoding techniques for LDPC codes presented here provides flexibility in selecting the appropriate scheme from performance, latency, computational-complexity, and memory-requirement perspectives.