Invited paper Picture processing using multiple-valued logic

The multi-valued logic, MVL, simply is a more generalized form of binary, or two valued, logic. It is an obvious advantage to process a signal in more than two levels from the information content point of view. Many logical and arithmetic functions are supposed to be more efficiently implemented with MVL. That is, fewer operations, gates, transistors, signal lines, etc., are required. However, it is a still complicated task to design a system for processing a signal in a multi-valued manner despite considerable effort. For taking the advantage of higher radix use, this obstacle should be overcome. The current-mode CMOS circuits have been considered the best candidate for implementation of MVL, because of their high speed and simpler circuit structures. In this thesis, an extended set of MVL operators is designed by using current-mode CMOS circuits. The key idea is that most MVL operators can be expressed in terms of basic algebraic descriptions. A new max gate is proposed as a disjunctive operator for propositional MVL descriptions. Besides, two new current-mode threshold circuits are constructed. With these, novel literal and cyclic structures are developed for, respectively, propositional, and closed-field realizations of MVL functions. A novel level restoration architecture is also proposed for reliable current-mode MVL applications. Designed circuits are shown to exhibit better performance compared to previous MVL designs. The proposed topologies are evaluated with such high-level designs as multiplexer, full-adder and multiplier, for radix-8. A novel higher-radix multiplication algorithm based on data set relocation into two or one quadrant of the multiplication chart is proposed, similar to Booth’s encoding in two-valued multiplication. The designed systems are simulated and compared to previous designs and their binary counterparts to show their superiority.

2005

The task of logic synthesis is to convert the logic description of set function into a netlist of gates that implements the functions. This paper describes the possibility of implementing some combinational and sequential circuits with multiple-valued PLAs (MVPLA), by multiple-valued multiplexers (MVLMUX) or multi-valued switches. The algorithms are based on multiple-valued decision diagrams (MDD) representation of the functions. The developed methodology offers some elegant algorithms that automatically map a MMD functions representation in to some certain multi-valued physic circuits. Also, these algorithms convert high logical functions representations into a lower one, very useful taking into account technological restrictions.

IEEE Micro, 2002

This article proposes using symbolic learning methods based on multiple-valued (MV) logic and implemented in reconfigurable hardware. In the part one, we discussed why symbolic learning is useful in some applications, such as robotics. We presented an architecture for a massively parallel reconfigurable processor that enables speeding up logic operations performed in learning hardware.

arXiv (Cornell University), 2013

This is to certify that this Project entitled "Multivalued Logic Circuit Design for Binary Logic Interface" has been successfully carried out by Hitesh Gupta (Enrolment No.: 09E2UCCSM4XP606), under my supervision and guidance, in partial fulfilment of the requirement for the award of Master of Technology degree in Computer Science &

Computer scientists, computer engineers, applied mathematicians, and physicists are familiar with options in which there are no middle choices between true and false. Statisticians are familiar with the soft logic of probability, and physicists are familiar with the logic of uncertainty. The lack of such choices is inconvenient and critical when trying to determine whether the status of a computer system is go, wait, or no-go. Multiple-valued logic is concerned with these intermediate choices. The major drawback to overcomplicated flowcharts developed by computer programmers is the difficulty with which they are checked, corrected, or modified. This situation suggests a structured design approach, where a structured flowchart or well designed program is built up to an adequate level of detail according to definite rules from a small, simple, and sufficient set of elemental blocks or primitives. Developments in multiple-valued logic as related to computer science include a range of disciplines in which comparisons to multiple-valued logic and computer science are being made, such as neural science and ethology.

2016

The utilization of Multiple-Valued Logic (MVL) in logic circuits has the potential to reduce the number of logic elements and interconnections that connect different parts of the circuit. With the reduction of the interconnections, delays, area and energy consumption can be reduced. In this thesis we propose a technology mapping tool that implements circuits using recently proposed 2-input Quaternary Lookup Tables (QLUTs), taking advantage of the benefits of MVL to produce more efficient circuits. The mapping functionality was implemented using MVSIS as a base platform. MVSIS reads the circuit specification from a file and creates a network representation, which is then used by the tool we developed to perform the decomposition of the network and mapping into the target technology. Overall, the results show a reduction in the number of interconnections, but this is offset by the increase in occupied area by the Lookup Tables (LUTs), due to the fact that a QLUT requires more transist...

To achieve the reduction of power consumption, optimizations are required at various levels of the design steps such as algorithm, architecture, logic and circuit & process techniques. This paper considers the two logic level approaches for low power digital design. Optimization techniques are carried to reduce switching activity power of individual logic-gates. we can reduce the power by using either circuit level optimization or logical level optimization. In this paper, the circuit level optimization process is followed to reduce the area and power. In the first approach, Modified gate diffusion input (GDI) logic is used in the proposed parallel asynchronous self time adder (PASTA) technique. Similarly, the structure of XOR gate and half adder is reduced to achieve the low area and low power. In second approach, Multi value logic based digital circuit is designed by increasing the representation domain from the two level (N=2) switching algebra to N > 2 levels. The main advantage of this approach is to compensate the inefficiency of existing integrated circuits that are used to implement the universal set of MVL gates. From the results, the proposed GDL logic based Adder offers less number of transistors (area) and low power consumption than the existing technique. And proposed MVL technique allows designing MVL digital circuit that is set to obtain the values from the binary circuits. Also this technique offers low power and small wiring delay, when compared to binary and three value logic. The simulation process is carried out by tanner toolv14.11 to check the functionality of the PASTA & MVL circuits. A. Proposed Modified Gdi Logic In day today life, the Systems on Chip (SoC) product are necessary. Millions of chip integrated into one single chip is called as SoC. These millions of chip are integrated into single chip by shrinking the transistor size in each and every chip. Therefore this CMOS technique can apply in SoC product [3]. Carry Select Adder (CSLA) is primarily used to minimize the chip size and for reducing the propagation delay. The parallel asynchronous self time adder (PASTA) is working based on iterative coding. So the number of unwanted activation of clock cycle is removed in this adder to achieve the high speed and low power. This type of adder will be designed in this paper in two ways [10]. The Gate Diffusion Input (GDI) technique is proposed in 2002 to reduce the area and power of VLSI digital circuits. The GDI logic was initially proposed for fabrication in twin-well and Silicon on Insulator (SOI) CMOS methods. It enabled the implementation of a broad range of difficult logic functions using simply two transistors. This scheme was appropriate for the design of regular digital circuits, with a much lower area than existing PTL and Static CMOS methods, whereas offering improved power characteristics. Equally to PTL implementations, the GDI circuits suffered from a decreased swing because of threshold drops. Conversely, a considerably shrinked the logic flexibility and transistor count of the basic GDI cell, gives major power reduction, in spite of the need for swing restoration circuits [1]. B. Proposed MVL Logic The MVL is also known as multiple-valued, multi-valued or many-valued logic that traces its origins back to the Lukasiewicz logic and Post algebra. The proposed methodology in this work is based on a universal set of gates that is used to implement operators acting on the elements of a domain. The current trend in Integrated Circuits (IC) is to embed multiple systems onto a single IC, known as System on a Chip (SoCs) leading to, factors like, an increment in the quantity, the delay time, length, and complexity of the interconnections. The multiple-valued logic is a viable alternative to cope up with the issues due to interconnections, as they are said to decrease the number of the interconnections. This reduction in the area of the IC devoted to the interconnections has motivated many MVL proposals. Methodologies for the synthesis of MVL digital circuits comprise of the operators and their properties. Main drawbacks of such methodologies are: first, the lack of existing integrated circuits that implement the universal set of gates and, second minimization tools needed to design practical MVL digital circuits.

IEEE Transactions on Computers, 2000

A family of multiple-valued (MV) electronic memo-CYCLE: AB -A plus B, mod N ry elements, referred to herein as flip-flops, is presented along with a system of MV algebra upon which they are based. These COMPLEMENT: A = P -A where P = N -1. MV flip-flops are compared to binary flip-flops. MV asynchronous set-clear flip-flops and synchronous set-clear, D-type, JK, Here, N = base of algebra (N > 2) and the logic values and modulo N counter flip-flops are presented, their next-state for A and B range from 0 through P. The Postian sysequations are derived, and they are shown to have desirable tem of algebra consists of operators AND, OR, and properties for use in MV sequential circuits. Experimental re-CYCLE and is functionally complete for any N 2 sults and schematic diagrams are presented for a level restoring three-valued logic gate, the clocked set-clear flip-flop, and an COMPLEMENT operator is included here to simplify the example synchronous sequential circuit. description of the MV flip-flops. Index Terms-Multiple-valued flip-flops, multiple-valued

International Journal of Computer Applications, 2014

A Multi Logic Memory cell have various logic between one and zero that's why fuzzy logic is also known as multiplelogic level, when the paper work was in plan originally plan was do something in Fuzzy Electronics. Lots of fuzzy systems is been developed already but from observing fuzzy flip-flops working the idea comes for the proposed work. Paper work propose designs of a new fuzzy memory cell(flip-flop) for four logic levels which can hold Logic 0, Logic 1, Logic 2 & Logic 3 total four fix logic .though fuzzy logic deals with approximate logic rather than fix proposed work has fix logic and it is the big difference between proposed work and fuzzy based memory cell. Proposed work also has design an Interfacing module between fuzzy memory with Digital) systems, just for make proposed four logic flip-flop compatible with existing binary logic based digital system application for proposed design that one can reduce the no. of wires required when to establish parallel interface with memory and also one can increase the speed or throughput of simple serial data transfer.

Tehnicki vjesnik - Technical Gazette, 2018

In the recent years, there were major importance to Multiple Valued Logic (MVL), where the most common reasons for considering the implementation of MVL circuits better then binary valued circuits are that reducing wiring congestion as compared to binary circuits, using a single conductor to transmit three or more discrete voltage or current values allows for greater information content per wire and the circuit cost models would be more economical. Therefore, in this paper the MVL concepts have been used to design 4-bit quaternary MVL Arithmetic and Logic Unit, which is considered a basic unit of a MVL microprocessor. It is the "heart" of a microprocessor and we could say that everything else in the microprocessor is there to support the ALU. The proposed Arithmetic and Logic Unit will do the operations as Addition, Subtraction, Maximum, Minimum and Invert. Simulation Program with Integrated Circuit Emphasis (SPICE) tool in Cadence simulator used in simulation the proposed Arithmetic and Logic Unit. The simulation results tells that the design is more efficient compared with the binary ALU and the circuit will be less area and less number of transistors.