On the Gardner Problem for Phase-Locked Loops

MILCOM 88, 21st Century Military Communications - What's Possible?'. Conference record. Military Communications Conference

Typical implementations of a phase-lock loop (PLL) are second order. In this paper we examine the advantages and disadvantages of a third order phase-lock loop. Among the advantages is more design freedom which can result in superior noise rejection and lower steady-state error than a second order PLL. Chief among the disadvantages of the third order PLL is the difficulty of analyzing its stability in the region of nonlinear operation. In this paper we will treat the third order PLL as a nonlinear control system: first examining the small signal (linear) operation and then extending the analysis to the nonlinear region. A useful set of tools from the nonlinear control system world, the second method of Lyapunov and LaSalle's Theorem, will be used to derive stability conditions for the nonlinear model.

SPIE Proceedings, 2005

In this paper a new stable high order Digital Phase Lock Loop (DPLL) design technique is proposed. This technique uses linear theory to design the DPLL. The stability of the DPLL is guaranteed by placing a restriction on the system gain. This stability boundary is found by transforming the system transfer function to the Z-domain and plotting the root locus of the LPLL for values of gain where all the system poles lie inside the unit circle. The max value of gain where all the poles lie inside the unit circle is the stability boundary. It is shown that the stability boundary of the LPLL is comparable to the stability boundary of the DPLL. Finally where the above Bessel filter system produces slow lock, gear shifting of the DPLL components is considered. This allows the DPLL to start off with a wide loop bandwidth and switch to the narrow bandwidth once the system has locked.

Procedia Computer Science, 2019

This is a self-archived version of an original article. This version may differ from the original in pagination and typographic details.

VLSI Circuits and Systems II, 2005

In this paper a new stable high order Digital Phase Lock Loop (DPLL) design technique is proposed. This technique uses linear theory to design the DPLL. The stability of the DPLL is guaranteed by placing a restriction on the system gain. This stability boundary is found by transforming the system transfer function to the Z-domain and plotting the root locus of the LPLL for values of gain where all the system poles lie inside the unit circle. The max value of gain where all the poles lie inside the unit circle is the stability boundary. It is shown that the stability boundary of the LPLL is comparable to the stability boundary of the DPLL. Finally where the above Bessel filter system produces slow lock, gear shifting of the DPLL components is considered. This allows the DPLL to start off with a wide loop bandwidth and switch to the narrow bandwidth once the system has locked.

Journal of Vibroengineering

The pull-in range of phase locked loop (PLL) is a key parameter for evaluating the performance of the PLL circuit. It is defined as the maximum detuning frequency range where the loop locks. Different methods have been proposed for computing the pull-in range of phase locked loops in the absence of time delay. In this paper, the effect of time delay on the pull-in range of second-order phase locked loop as well as its dynamical behavior will be discussed. The time delay is modeled using first order Pade approximation. Using Pade approximation, the nonlinear second order delay differential equation which describes the phase error dynamic of the PLL is transformed into fourth order system in the state space representation. The new time-delay PLL model is simulated and different behavior is observed which is different than a typical PLL system without delay. As the gain of the loop increases, new behavior such as change of circuit stability and chaos are recognized which suggests that ...

Acta Mathematicae Applicatae Sinica, 1991

Computers & Mathematics with Applications, 2000

We examine the operation of the phase-lock loop (PLL). The PLL is one of the fundamental tools of the electrical engineer. It is nonlinear, and its operation is usually examined only after a number of simplifying assumptions are made. We derive an equation that governs this tool's operation and determine the properties of the solutions of the equation. We show that the linear time invariant approximation that is generally used to model the PLL is a good approximation to the original nonlinear time-varying equation.

Mathematical Problems in Engineering

Analysis of bifurcation of second-order analog phase locked loop (PLL) with tanlock and sawtooth phase detectors is investigated. Both qualitative and quantitative analyses are carried out. Qualitatively, the basin boundaries of the attractors were constructed by plotting the stable and the unstable manifolds of the system. The basin boundaries show that the PLL under consideration for certain loop parameters has a separatrix cycle which terminates the limit cycle (out-of-lock state) and the loop pulls-in. This behavior is known in literature as homoclinic bifurcation and the value of the bifurcation parameter where this process occurs is called the pull-in range. Quantitatively, we propose a collocation-based algorithm to compute the separatrix cycle and the pull-in range. The separatrix cycle is approximated by a finite set of harmonics N with unknown amplitudes and by utilizing the fact that this limit cycle bifurcates from a separatrix cycle, a system of nonlinear algebraic equa...

2014

Phase-locked loops (PLL) have found applications in many industrial applications such as communication and control systems. The key requirements are stability and loop performance in terms of signal-to-noise ratio and tracking errors. Here we present a two-step approach to PLL design. First, we present a Lyapunov approach to analyze the loop stability. The parameter range that can guarantee stability can be easily derived in the process. Second, we present a multi-objective optimization method that can search a set of values within the above range of parameters to achieve an optimal trade-off between loop bandwidth, transient and steady-state performance. Simulation results are contained to illustrate the performance of our procedure.

2004

The chaos induced in a new type of phase locked loop (PLL) having a second-order loop filter is investigated. The system under consideration is modeled as a third-order autonomous system with sinusoidal phase detector characteristics. The modern of nonlinear theory such as bifurcation and chaos is applied to a third-order of PLL. A method is developed to quantitatively study the type of bifurcations that occur in this type of PLLÕs. The study showed that PLL experiencing a Hopf bifurcation point as well as chaotic behaviour. The method of multiple scales is used to find the normal form near the Hopf bifurcation point. The point is found to be supercritical one.

IEEE Transactions on Circuits and Systems II: Express Briefs, 2000

The analysis, and design of 3 rd order, (and higher) Phase-Locked Loops (PLL) is difficult. This paper presents a novel approach to overcome these difficulties by allowing high order loops to be viewed as a natural extension of lower order ones. This is accomplished by adding nested first-order feedback loops around a basic first-order Loop Filter. Our approach will also be related to the concept of PLLs with aided acquisition. The model presented has been implemented and tested in Simulink®.

2013 Formal Methods in Computer-Aided Design, 2013

We present a verification of a digital phase-locked loop (PLL) using the SpaceEx hybrid-systems tool. In particular, we establish global convergence-from any initial state the PLL eventually reaches a state of phase and frequency lock. Having shown that the PLL converges to a small region, traditional methods of circuit analysis based on linear-systems theory can be used to characterize the response of the PLL when in lock. The majority of the verification involves modeling each component of the PLL with piece-wise linear differential inclusions. We show how non-linear transfer functions, quantization error, and other non-idealities can be included in such a model. A limitation of piece-wise linear inclusions is that the linear coefficients for each component must take on fixed values. For real designs, ranges will be specified for these components. We show how a key step of the verification can be generalized to handle interval values for the linear coefficients by using an SMT solver.

Proceedings of the 2003 American Control Conference, 2003., 2003

The author has previously established that Lyapunov redesign is effective in designing an analog phase-locked loop for which the nonlinear model (in the signal phase space) is guaranteed to be stable [1]. This paper extends that concept to what are commonly called classical digital phase-locked loops [2]. These loops, which are very common in high speed digital communications systems, use digital phase detectors but analog filters and VCOs.

2006 IEEE International Symposium on Circuits and Systems, 2006

This paper examines the nonlinear dynamics of a model of a second order Bang-Bang Phase-Locked Loop (BB-PLL). Three distinct steady state dynamical patterns (locking, slew-rate limiting and limit cycles) have been observed for this discrete system. A corresponding continuous model of the BB-PLL is established. This paper focuses on the occurrence and the shape of the limit cycles. In particular, equations for the limit cycle trajectories are determined. The condition for the appearance of limit cycles is then established as a boundary in parameter space. A further theorem transfers this analysis back to the discrete system, where a continuum of cycles is found to occur. A direct relationship between the level of input phase deviation and the occurrence of limit cycles is observed. I.

Communications in Nonlinear Science and Numerical Simulation, 2017

Phase-locked loops (PLLs) are devices able to recover time signals in several engineering applications. The literature regarding their dynamical behavior is vast, specifically considering that the process of synchronization between the input signal, coming from a remote source, and the PLL local oscillation is robust. For high-frequency applications it is usual to increase the PLL order by increasing the order of the internal filter, for guarantying good transient responses; however local parameter variations imply structural instability, thus provoking a Hopf bifurcation and a route to chaos for the phase error. Here, one usual architecture for a third-order PLL is studied and a range of permitted parameters is derived, providing a rule of thumb for designers. Out of this range, a Hopf bifurcation appears and, by increasing parameters, the periodic solution originated by the Hopf bifurcation degenerates into a chaotic attractor, therefore, preventing synchronization.