Exploring FPGA Routing Architecture Stochastically

2007 25th International Conference on Computer Design, 2007

Systems with the combined features of ASICs and Field Programmable Gate Arrays(FPGAs) are increasingly being considered as technology forerunners looking at their extraordinary benefits. This drags FPGAs into the technology scaling race along with ASICs exposing the FPGA industries to the problems associated with scaling. Extensive process variations is one such issue which directly impacts the profit margins of hardware design beyond 65nm gate length technology. Since the resources in FPGAs are primarily dominated by the interconnect fabric, variations in the interconnect impacting the critical path timing and leakage yield needs rigorous analysis. In this work we provide a statistical modeling of individual routing components in an FPGA followed by a statistical methodology to analyze the timing and leakage distribution. This statistical model is incorporated into the routing algorithm to model a new Statistically Intelligent Routing Algorithm(SIRA), which simultaneously optimizes the leakage and timing yield of the FPGA device. We demonstrate and average leakage yield increase of 9% and timing yield by 11% using our final algorithm.

Proceedings of the 16th international ACM/SIGDA symposium on Field programmable gate arrays, 2008

Architecture development for FPGAs has typically been a very empirical discipline, requiring the synthesis of benchmark circuits into candidate architectures. This is difficult to do in the early stages of architecture development, however, because there is no complete architecture to synthesize circuits into. The effort required to create prototype tools for nascent architectures is far too great for every new logic block or routing architecture idea, and so it would be extremely helpful to have a simple and intuitive FPGA interconnect model to guide the architect. In this paper we present such an interconnect model for island-style FPGAs, whose single output is the estimated routing demand (often referred to as W, the number of routing tracks per channel) for an FPGA as a function of several logic block, circuit and routing architecture parameters. The goal of this model is to be as simple as possible, while still accurate enough to be useful, to provide understanding and intuition on FPGA routing. Our methodology is empirical-we propose model forms based on empirical observations, intuition and some derivation, and then fit models to experimentally generated data. We show the development of the model in stages, beginning with a fully flexible FPGA, and gradually proceeding to one which includes the key parameters that control the flexibility of FPGA routing, and one key parameter describing the logic block and another relating to the typical circuit. We then show how to use these models in early-stage architecture development to provide feedback on several aspects of logic block architecture. We also show how the model can be used to explore the routing architecture space itself and to provide an overall intuition for architecture development.

2000

Multi-FPGA boards are being used for logic emulation, rapid prototyping, custom computing and low volume subsystem implementation. A key feature which characterizes these boards is their routing architecture(RA). Inter-FPGA connections in an RA can be of two types, namely fixed connections through direct wires and programmable connections through intermediate Field-Programmable Interconnect Devices. This paper presents an analytical approach for evaluating routing performance of an RA employing both types of connections . Our approach consists of two steps: 1) Generation of random interconnection requirement matrix for modeling real circuits with an orientation towards the available interconnection architecture. 2) Checking the routability of the generated matrix on the given RA.

This paper describes a new detailed routing algorithm, speciffically designed for those types of architecturesthat are found on the most recent generations of Field-Programmable Gate Arrays (FP-GAs). The algorithm, called RAISE, can be applied to a broad range of optimizations problems and has been used for detailed routing of symmetrical FPGAs, whose routing architecture consists of rows and columns of logic cells interconnected by routing channels. RAISE (Router using AadaptIve Simulated Evolution) searches not only for a possible solution, but tries to find the one with minimum delay. Excelent routing results have been obtained over a set of several benchmark circuits getting solutions close to the minimum number of tracks.

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1997

This paper presents a new performance and routability driven router for symmetrical array based field programmable gate arrays (FPGA's). The objectives of our proposed routing algorithm are twofold: 1) improving the routability of the design (i.e., minimizing the maximum required routing channel density) and 2) improving the overall performance of the design (i.e., minimizing the overall path delay). Initially, nets are routed sequentially according to their criticalities and routabilities. The nets/paths violating the routing-resource and timing constraints are then resolved iteratively by a rip-up-and-rerouter, which is guided by a simulated evolution based optimization technique. The proposed algorithm considers the path delays and routability throughout the entire routing process. Experimental results show that our router can significantly improve routability and reduce delay over many existing routing algorithms.

2009 International Conference on Field-Programmable Technology, 2009

This paper optimizes the routing structure for hybrid FPGAs, in which high I/O density coarse-grained units are embedded within fine-grained logic. This significantly increases the routing resource requirement between elements. We investigate the routing demand for hybrid FPGAs over a set of domainspecific applications. The trade-off in delay, area and routability of the separation distance between coarse-grained blocks are studied. The effects of adding routing switches to the coarsegrained blocks and using wider channels near them to meet extra routing demand are examined. Our optimized architectures are compared to existing column based architecture. The results show that (1) there is 44% tracks usage at the edge of the embedded blocks, (2) both the separation of embedded blocks and addition of switches to embedded blocks can increase the area and delay performance by 48.4% compared to column based FPGA architecture, (3) wider channel width reduces the area of highly congested system by 34.9%, but it cannot further improve the system with separation of embedded blocks and additional switches on embedded blocks.

Proceedings of the 2005 international workshop on System level interconnect prediction - SLIP '05, 2005

The interconnection architecture of FPGAs such as switches dominates performance of FPGAs. Three-dimensional integration of FPGAs overcomes interconnect limitations by allowing instances to be located and signals to be routed in 3-D space. Wire resource prediction is important for fast and accurate interconnection planning in 3-D FPGA. In this paper, we extend the existing analytic model shown in [13] with a new parameter for our 3-D FPGA which has clusterbased logic blocks. The proposed wire resource prediction model is applied to our 3-D FPGA using a Xilinx Virtex2 slice [18] and our 3-D routing architecture. We validate the effectiveness of the extended model by comparing the required number of channel wires predicted by the extended analytic equation with that of the placed and routed results using 3-D placement and routing algorithm designed for our 3-D FPGA for a number of benchmark circuits. The extended 3-D wire resource prediction model predicts the required channel capacity with an average of 11.1% error for 17 large circuits from LGSynth93 and ISPD2001 Verilog benchmarks.

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2000

In this paper, the routing problem for twodimensional (2-D) field programmable gate arrays of a Xilinx-like architecture is studied. We first propose an efficient one-step router that makes use of the main characteristics of the architecture. Then we propose an improved approach of coupling two greedy heuristics designed to avoid an undesired decaying effect, a dramatically degenerated router performance on the near completion stages. This phenomenon is commonly observed on results produced by the conventional deterministic routing strategies using a single optimization cost function. Consequently, our results are significantly improved on both the number of routing tracks and routing segments by just applying low-complexity algorithms. On the tested MCNC and industrial benchmarks, the total number of tracks used by the best known two-step global/detailed router is 28% more than that used by our proposed method.

VLSI Design, 1998

This paper presents a performance-oriented placement and routing tool for fieldprogrammable gate arrays. Using recursive geometric partitioning for simultaneous placement and global routing, and a graph-based strategy for detailed routing, our tool optimizes source-sink pathlengths, channel width and total wirelength. Our results compare favorably with other FPGA layout tools, as measured by the maximum channel width required to place and route several benchmarks.

Proceedings - 2006 International Conference on Field Programmable Logic and Applications, FPL, 2006

The novel methodology for designing a high-performance and low-energy FPGA interconnection architecture consisting of appropriate wire segments and multiple Switch Boxes is introduced. Depending on the localized performance and energy consumption requirements of each specific region of FPGA architecture, we derive a set of corresponding spatial routing information of the applications mapped onto reconfigurable device. In this paper, an interconnection network with segments L1&L2 and 3 different Switch Box regions is used. The selection criterion for our approach is the minimal Energy×Delay Product (EDP). The proposed methodology is fullysupported by the software tool called EX-VPR. With this interconnection architecture we achieved EDP reduction by 56%, performance increase by 47%, reduction in leakage power by 18%, reduction in total energy consumption by 9%, at the expense of increase of channel width by 15% compared to conventional FPGA architectures.